ramips: Add support for ZBT-CPE102

- CPU: MT7620N 580MHz
- Flash: 8MB
- RAM: 64MB
- build-in minipcie slot for modem 3G/4G
- one ethernet port 10/100Mbps

Signed-off-by: Cezary Jackiewicz <cezary@eko.one.pl>

1 files changed, 118 insertions, 0 deletions

diff --git a/target/linux/ramips/dts/ZBT-CPE102.dts b/target/linux/ramips/dts/ZBT-CPE102.dts
new file mode 100644
index 0000000000..b93e58526a
--- /dev/null
+++ b/target/linux/ramips/dts/ZBT-CPE102.dts
@@ -0,0 +1,118 @@
+/dts-v1/;
+
+#include "mt7620n.dtsi"
+
+/ {
+	compatible = "zbtlink,zbt-cpe102", "ralink,mt7620n-soc";
+	model = "Zbtlink ZBT-CPE102";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		4g-0 {
+			label = "zbt-cpe102:green:4g-0";
+			gpios = <&gpio1 14 1>;
+		};
+
+		4g-1 {
+			label = "zbt-cpe102:green:4g-1";
+			gpios = <&gpio0 2 1>;
+		};
+
+		4g-2 {
+			label = "zbt-cpe102:green:4g-2";
+			gpios = <&gpio1 15 1>;
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <20>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 1 1>;
+			linux,code = <0x198>;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	en25q64@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		linux,modalias = "m25p80";
+		spi-max-frequency = <10000000>;
+
+		partition@0 {
+			label = "u-boot";
+			reg = <0x0 0x30000>;
+			read-only;
+		};
+
+		partition@30000 {
+			label = "u-boot-env";
+			reg = <0x30000 0x10000>;
+			read-only;
+		};
+
+		factory: partition@40000 {
+			label = "factory";
+			reg = <0x40000 0x10000>;
+			read-only;
+		};
+
+		partition@50000 {
+			label = "firmware";
+			reg = <0x50000 0x760000>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&ethernet {
+	mtd-mac-address = <&factory 0x4>;
+	mediatek,portmap = "wllll";
+};
+
+&wmac {
+	ralink,mtd-eeprom = <&factory 0>;
+};
+
+&pinctrl {
+	state_default: pinctrl0 {
+		default {
+			ralink,group = "i2c", "spi refclk", "wled";
+			ralink,function = "gpio";
+		};
+	};
+};