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authorStanislav Galabov <stanislav_galabov@smartcom.bg>2016-05-10 13:41:46 +0300
committerJohn Crispin <john@phrozen.org>2016-05-12 03:29:35 +0200
commit9195d8da355d0d141ac02c9a5269452dc64ffd2d (patch)
tree6983c73be89b47cc24300c4771618d01fa4ba901 /target/linux/ramips/dts/UBNT-ERX.dts
parent861266c9ec0d5a48af044a08a01ccb9fc62b1ac8 (diff)
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ramips: DTS rework
Add node aliases to dtsi files. Reword dts files so they're more in-line with upstream. Fix some more warnings and errors reported by dtc Signed-off-by: Stanislav Galabov <sgalabov@gmail.com>
Diffstat (limited to 'target/linux/ramips/dts/UBNT-ERX.dts')
-rw-r--r--target/linux/ramips/dts/UBNT-ERX.dts88
1 files changed, 43 insertions, 45 deletions
diff --git a/target/linux/ramips/dts/UBNT-ERX.dts b/target/linux/ramips/dts/UBNT-ERX.dts
index ec31a37f0b..713519d5d9 100644
--- a/target/linux/ramips/dts/UBNT-ERX.dts
+++ b/target/linux/ramips/dts/UBNT-ERX.dts
@@ -17,30 +17,6 @@
bootargs = "console=ttyS0,57600";
};
- palmbus@1E000000 {
- spi@b00 {
- /* This board has 2Mb spi flash soldered in and visible
- from manufacturer's firmware.
- But this SoC shares spi and nand pins,
- and current driver does't handle this sharing well */
- status = "disabled";
- m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <1>;
- linux,modalias = "m25p80";
- spi-max-frequency = <10000000>;
-
- partition@0 {
- label = "spi";
- reg = <0x0 0x200000>;
- read-only;
- };
- };
- };
- };
-
nand@1e003000 {
status = "okay";
@@ -78,27 +54,6 @@
};
- ethernet@1e100000 {
- mtd-mac-address = <&factory 0x22>;
- };
-
- pinctrl {
- state_default: pinctrl0 {
- gpio {
- ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag";
- ralink,function = "gpio";
- };
- };
- };
-
- sdhci@1E130000 {
- status = "disabled";
- };
-
- pcie@1e140000 {
- status = "disabled";
- };
-
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
@@ -112,3 +67,46 @@
};
};
};
+
+&ethernet {
+ mtd-mac-address = <&factory 0x22>;
+};
+
+&pinctrl {
+ state_default: pinctrl0 {
+ gpio {
+ ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag";
+ ralink,function = "gpio";
+ };
+ };
+};
+
+&sdhci {
+ status = "disabled";
+};
+
+&pcie {
+ status = "disabled";
+};
+
+&spi0 {
+ /* This board has 2Mb spi flash soldered in and visible
+ from manufacturer's firmware.
+ But this SoC shares spi and nand pins,
+ and current driver does't handle this sharing well */
+ status = "disabled";
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ linux,modalias = "m25p80";
+ spi-max-frequency = <10000000>;
+
+ partition@0 {
+ label = "spi";
+ reg = <0x0 0x200000>;
+ read-only;
+ };
+ };
+};