[pxa]: upgrade to 2.6.32.7, switch to squashfs, remove broken flag

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19562 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 0 insertions, 113 deletions

diff --git a/target/linux/pxa/patches-2.6.21/009-bkpxa-pxa-cpu.patch b/target/linux/pxa/patches-2.6.21/009-bkpxa-pxa-cpu.patch
deleted file mode 100644
index 72480612cd..0000000000
--- a/target/linux/pxa/patches-2.6.21/009-bkpxa-pxa-cpu.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-Status: WORKS
-PXA CPU enhancements
-
-from patch 1667:
-- 64K PTEs
-from hh.org-cvs:
-- support in pxa_gpio_mode for active low
-
-#
-# Patch managed by http://www.mn-logistik.de/unsupported/pxa250/patcher
-#
-
---- a/arch/arm/mm/proc-xscale.S
-+++ b/arch/arm/mm/proc-xscale.S
-@@ -474,11 +474,62 @@ ENTRY(cpu_xscale_set_pte_ext)
- 	movne	r2, #0				@ no -> fault
- 
- 	str	r2, [r0]			@ hardware version
-+
-+	@ We try to map 64K page entries when possible.  
-+	@ We do that for kernel space only since the usage pattern from
-+	@ the setting of VM area is quite simple.  User space is not worth
-+	@ the implied complexity because of ever randomly changing PTEs 
-+	@ (page aging, swapout, etc) requiring constant coherency checks.
-+	@ Since PTEs are usually set in increasing order, we test the
-+	@ possibility for a large page only when given the last PTE of a
-+	@ 64K boundary.
-+	tsteq	r1, #L_PTE_USER
-+	andeq	r1, r0, #(15 << 2)
-+	teqeq	r1, #(15 << 2)
-+	beq	1f
-+
- 	mov	ip, #0
- 	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
- 	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
- 	mov	pc, lr
- 
-+	@ See if we have 16 identical PTEs but with consecutive base addresses
-+1:	bic	r3, r2, #0x0000f000
-+	mov	r1, #0x0000f000
-+2:	eor	r2, r2, r3
-+	teq	r2, r1
-+	bne	4f
-+	subs	r1, r1, #0x00001000
-+	ldr	r2, [r0, #-4]!
-+	bne	2b
-+	eors	r2, r2, r3
-+	bne	4f
-+
-+	@ Now create our LARGE PTE from the current EXT one.
-+	bic	r3, r3, #PTE_TYPE_MASK
-+	orr	r3, r3, #PTE_TYPE_LARGE
-+	and	r2, r3, #0x30			@ EXT_AP --> LARGE_AP0
-+	orr	r2, r2, r2, lsl #2		@ add LARGE_AP1
-+	orr	r2, r2, r2, lsl #4		@ add LARGE_AP3 + LARGE_AP2
-+	and	r1, r3, #0x3c0			@ EXT_TEX
-+	bic	r3, r3, #0x3c0
-+	orr	r2, r2, r1, lsl #(12 - 6)	@ --> LARGE_TEX
-+	orr	r2, r2, r3			@ add remaining bits
-+
-+	@ then put it in the pagetable
-+	mov	r3, r2
-+3:	strd	r2, [r0], #8
-+	tst	r0, #(15 << 2)
-+	bne	3b
-+
-+	@ Then sync the 2 corresponding cache lines
-+	sub	r0, r0, #(16 << 2)
-+	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
-+4:	orr	r0, r0, #(15 << 2)
-+	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
-+	mov	ip, #0
-+	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
-+	mov	pc, lr
- 
- 	.ltorg
- 
---- a/include/asm-arm/arch-pxa/pxa-regs.h
-+++ b/include/asm-arm/arch-pxa/pxa-regs.h
-@@ -1345,6 +1345,7 @@
- #define GPIO_ALT_FN_2_OUT	0x280
- #define GPIO_ALT_FN_3_IN	0x300
- #define GPIO_ALT_FN_3_OUT	0x380
-+#define GPIO_ACTIVE_LOW         0x1000
- #define GPIO_MD_MASK_NR		0x07f
- #define GPIO_MD_MASK_DIR	0x080
- #define GPIO_MD_MASK_FN		0x300
-@@ -1597,6 +1598,25 @@
- #define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */
- #define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */
- 
-+#define PWER_GPIO(Nb)	(1 << Nb)	/* GPIO [0..15] wake-up enable     */
-+#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable        */
-+#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable        */
-+#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable        */
-+#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable        */
-+#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable        */
-+#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable        */
-+#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable        */
-+#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable        */
-+#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable        */
-+#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable        */
-+#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable        */
-+#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable        */
-+#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable        */
-+#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable        */
-+#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable        */
-+#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */
-+#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */
-+
- 
- /*
-  * SSP Serial Port Registers