backport support of the OpenRB Lite board to 2.6.28

SVN-Revision: 16912

1 files changed, 340 insertions, 0 deletions

diff --git a/target/linux/ppc40x/patches/007-openrb-light.patch b/target/linux/ppc40x/patches/007-openrb-light.patch
new file mode 100644
index 0000000000..faafbb8400
--- /dev/null
+++ b/target/linux/ppc40x/patches/007-openrb-light.patch
@@ -0,0 +1,340 @@
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -70,7 +70,8 @@ src-plat := of.c cuboot-52xx.c cuboot-82
+ 		cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
+ 		cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
+ 		virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
+-		cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c
++		cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c \
++		cuboot-openrb-light.c
+ src-boot := $(src-wlib) $(src-plat) empty.c
+ 
+ src-boot := $(addprefix $(obj)/, $(src-boot))
+@@ -216,6 +217,7 @@ image-$(CONFIG_WALNUT)			+= treeImage.wa
+ image-$(CONFIG_ACADIA)			+= cuImage.acadia
+ image-$(CONFIG_MAGICBOXV1)		+= cuImage.magicboxv1
+ image-$(CONFIG_MAGICBOXV2)		+= cuImage.magicboxv2
++image-$(CONFIG_OPENRB_LIGHT)		+= cuImage.openrb-light
+ 
+ # Board ports in arch/powerpc/platform/44x/Kconfig
+ image-$(CONFIG_EBONY)			+= treeImage.ebony cuImage.ebony
+--- a/arch/powerpc/platforms/40x/Kconfig
++++ b/arch/powerpc/platforms/40x/Kconfig
+@@ -79,6 +79,16 @@ config MAKALU
+ 	help
+ 	  This option enables support for the AMCC PPC405EX board.
+ 
++config OPENRB_LIGHT
++	bool "OpenRB Light"
++	depends on 40x
++	default n
++	select PPC40x_SIMPLE
++	select 405EP
++	select PCI
++	help
++	  This option enables support for the OpenRB Light board.
++
+ #config REDWOOD_5
+ #	bool "Redwood-5"
+ #	depends on 40x
+--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
++++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
+@@ -54,6 +54,7 @@ static char *board[] __initdata = {
+ 	"amcc,acadia",
+ 	"magicboxv1",
+ 	"magicboxv2",
++	"openrb,light",
+ };
+ 
+ static int __init ppc40x_probe(void)
+--- /dev/null
++++ b/arch/powerpc/boot/cuboot-openrb-light.c
+@@ -0,0 +1,41 @@
++/*
++ * Old U-boot compatibility for OpenRB Light board
++ *
++ * Author: Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include "ops.h"
++#include "io.h"
++#include "dcr.h"
++#include "stdio.h"
++#include "4xx.h"
++#include "44x.h"
++#include "cuboot.h"
++
++#define TARGET_4xx
++#define TARGET_405EP
++#include "ppcboot.h"
++
++static bd_t bd;
++
++static void openrb_light_fixups(void)
++{
++	ibm405ep_fixup_clocks(33333000);
++	ibm4xx_sdram_fixup_memsize();
++	dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
++}
++
++void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
++		unsigned long r6, unsigned long r7)
++{
++	CUBOOT_INIT();
++	platform_ops.fixups = openrb_light_fixups;
++	platform_ops.exit = ibm40x_dbcr_reset;
++	fdt_init(_dtb_start);
++	serial_console_init();
++}
++
+--- /dev/null
++++ b/arch/powerpc/boot/dts/openrb-light.dts
+@@ -0,0 +1,244 @@
++/*
++ * Device Tree Source for OpenRB Light board
++ *
++ * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Based on magicboxv2.dts
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without
++ * any warranty of any kind, whether express or implied.
++ */
++
++/dts-v1/;
++
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	model = "openrb,light";
++	compatible = "openrb,light";
++	dcr-parent = <&{/cpus/cpu@0}>;
++
++	aliases {
++		ethernet0 = &EMAC0;
++		serial0 = &UART0;
++		serial1 = &UART1;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu@0 {
++			device_type = "cpu";
++			model = "PowerPC,405EP";
++			reg = <0x00000000>;
++			clock-frequency = <0xbebc200>; /* Filled in by zImage */
++			timebase-frequency = <0>; /* Filled in by zImage */
++			i-cache-line-size = <20>;
++			d-cache-line-size = <20>;
++			i-cache-size = <4000>;
++			d-cache-size = <4000>;
++			dcr-controller;
++			dcr-access-method = "native";
++		};
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x00000000 0x00000000>; /* Filled in by zImage */
++	};
++
++	UIC0: interrupt-controller {
++		compatible = "ibm,uic";
++		interrupt-controller;
++		cell-index = <0>;
++		dcr-reg = <0x0c0 0x009>;
++		#address-cells = <0>;
++		#size-cells = <0>;
++		#interrupt-cells = <2>;
++	};
++
++	plb {
++		compatible = "ibm,plb3";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
++		clock-frequency = <0>; /* Filled in by zImage */
++
++		SDRAM0: memory-controller {
++			compatible = "ibm,sdram-405ep";
++			dcr-reg = <0x010 0x002>;
++		};
++
++		MAL: mcmal {
++			compatible = "ibm,mcmal-405ep", "ibm,mcmal";
++			dcr-reg = <0x180 0x062>;
++			num-tx-chans = <4>;
++			num-rx-chans = <2>;
++			interrupt-parent = <&UIC0>;
++			interrupts = <
++				0xb 0x4 /* TXEOB */
++				0xc 0x4 /* RXEOB */
++				0xa 0x4 /* SERR */
++				0xd 0x4 /* TXDE */
++				0xe 0x4 /* RXDE */>;
++		};
++
++		OPB0: opb {
++			compatible = "ibm,opb-405ep", "ibm,opb";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0xef600000 0xef600000 0x00a00000>;
++			dcr-reg = <0x0a0 0x005>;
++			clock-frequency = <0>; /* Filled in by zImage */
++
++			UART0: serial@ef600300 {
++				device_type = "serial";
++				compatible = "ns16550";
++				reg = <0xef600300 0x00000008>;
++				virtual-reg = <0xef600300>;
++				clock-frequency = <0>; /* Filled in by zImage */
++				current-speed = <115200>;
++				interrupt-parent = <&UIC0>;
++				interrupts = <0x0 0x4>;
++			};
++
++			UART1: serial@ef600400 {
++				device_type = "serial";
++				compatible = "ns16550";
++				reg = <0xef600400 0x00000008>;
++				virtual-reg = <0xef600400>;
++				clock-frequency = <0>; /* Filled in by zImage */
++				current-speed = <115200>;
++				interrupt-parent = <&UIC0>;
++				interrupts = <0x1 0x4>;
++			};
++
++			IIC: i2c@ef600500 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "ibm,iic-405ep", "ibm,iic";
++				reg = <0xef600500 0x00000011>;
++				interrupt-parent = <&UIC0>;
++				interrupts = <0x2 0x4>;
++
++				eeprom@50 {
++					compatible = "at24,24c16";
++					reg = <0x50>;
++				};
++			};
++
++			GPIO0: gpio-controller@ef600700 {
++				compatible = "ibm,ppc4xx-gpio";
++				reg = <0xef600700 0x00000020>;
++				#gpio-cells = <2>;
++				gpio-controller;
++			};
++
++			EMAC0: ethernet@ef600800 {
++				linux,network-index = <0x0>;
++				device_type = "network";
++				compatible = "ibm,emac-405ep", "ibm,emac";
++				interrupt-parent = <&UIC0>;
++				interrupts = <
++					0xf 0x4 /* Ethernet */
++					0x9 0x4 /* Ethernet Wake Up */>;
++				local-mac-address = [000000000000]; /* Filled in by zImage */
++				reg = <0xef600800 0x00000070>;
++				mal-device = <&MAL>;
++				mal-tx-channel = <0>;
++				mal-rx-channel = <0>;
++				cell-index = <0>;
++				max-frame-size = <0x5dc>;
++				rx-fifo-size = <0x1000>;
++				tx-fifo-size = <0x800>;
++				phy-mode = "mii";
++				phy-map = <0x00000000>;
++			};
++
++			leds {
++				compatible = "gpio-leds";
++				user {
++					label = "openrb:green:user";
++					gpios = <&GPIO0 2 1>;
++				};
++			};
++		};
++
++		EBC0: ebc {
++			compatible = "ibm,ebc-405ep", "ibm,ebc";
++			dcr-reg = <0x012 0x002>;
++			#address-cells = <2>;
++			#size-cells = <1>;
++			/* The ranges property is supplied by the bootwrapper
++			 * and is based on the firmware's configuration of the
++			 * EBC bridge
++			 */
++			clock-frequency = <0>; /* Filled in by zImage */
++
++			nor_flash@ff800000 {
++				compatible = "cfi-flash";
++				bank-width = <2>;
++				reg = <0x00000000 0xff800000 0x00800000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				partition@0 {
++					label = "linux";
++					reg = <0x0 0x120000>;
++				};
++				partition@120000 {
++					label = "rootfs";
++					reg = <0x120000 0x6a0000>;
++				};
++				partition@7c0000 {
++					label = "u-boot";
++					reg = <0x7c0000 0x30000>;
++					read-only;
++				};
++			};
++		};
++
++		PCI0: pci@ec000000 {
++			device_type = "pci";
++			#interrupt-cells = <1>;
++			#size-cells = <2>;
++			#address-cells = <3>;
++			compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
++			primary;
++			reg = <0xeec00000 0x00000008    /* Config space access */
++			       0xeed80000 0x00000004    /* IACK */
++			       0xeed80000 0x00000004    /* Special cycle */
++			       0xef480000 0x00000040>;  /* Internal registers */
++
++			/* Outbound ranges, one memory and one IO,
++			 * later cannot be changed. Chip supports a second
++			 * IO range but we don't use it for now
++			 */
++			ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
++				  0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
++
++			/* Inbound 2GB range starting at 0 */
++			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
++
++			interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
++			interrupt-map = <
++				/* IDSEL 1 */
++				0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
++
++				/* IDSEL 2 */
++				0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
++
++				/* IDSEL 3 */
++				0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
++
++				/* IDSEL 4 */
++				0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
++			>;
++		};
++	};
++
++	chosen {
++		linux,stdout-path = "/plb/opb/serial@ef600300";
++	};
++};