oxnas: add 5.4 as testing kernel version

Add 5.4 kernel version as a new testing kernel option.
Run-tested on Shuttle KD20, seems to work just as well as kernel 4.14.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

1 files changed, 122 insertions, 0 deletions

diff --git a/target/linux/oxnas/patches-5.4/340-oxnas-pcie.patch b/target/linux/oxnas/patches-5.4/340-oxnas-pcie.patch
new file mode 100644
index 0000000000..19065233cf
--- /dev/null
+++ b/target/linux/oxnas/patches-5.4/340-oxnas-pcie.patch
@@ -0,0 +1,122 @@
+--- a/drivers/pci/controller/Kconfig
++++ b/drivers/pci/controller/Kconfig
+@@ -48,6 +48,11 @@ config PCIE_CADENCE_EP
+ 	  endpoint mode. This PCIe controller may be embedded into many
+ 	  different vendors SoCs.
+ 
++config PCIE_OXNAS
++	bool "PLX Oxnas PCIe controller"
++	depends on ARCH_OXNAS
++	select PCIEPORTBUS
++
+ endmenu
+ 
+ config PCIE_XILINX_NWL
+--- a/drivers/pci/controller/Makefile
++++ b/drivers/pci/controller/Makefile
+@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-r
+ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
+ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+ obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
++obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
+ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
+ obj-$(CONFIG_VMD) += vmd.o
+ # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -289,7 +289,7 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			compatible = "simple-bus";
+-			ranges = <0 0x47000000 0x1000000>;
++			ranges = <0 0x47000000 0x2000>;
+ 
+ 			scu: scu@0 {
+ 				compatible = "arm,arm11mp-scu";
+@@ -318,5 +318,86 @@
+ 				      <0x100 0x500>;
+ 			};
+ 		};
++
++		pcie0: pcie-controller@47c00000 {
++			compatible = "plxtech,nas782x-pcie";
++			device_type = "pci";
++			#address-cells = <3>;
++			#size-cells = <2>;
++
++			/*		flag & space	bus address	host address	size */
++			ranges = <	0x82000000	0 0x48000000	0x48000000	0 0x2000000
++					0xC2000000	0 0x4A000000	0x4A000000	0 0x1E00000
++					0x81000000	0 0x4BE00000	0x4BE00000	0 0x0100000
++					0x80000000	0 0x4BF00000	0x4BF00000	0 0x0100000>;
++
++			bus-range = <0x00 0x7f>;
++
++			/*	cfg			inbound translator	*/
++			reg =	<0x47c00000 0x1000>,	<0x47d00000 0x100>;
++
++			phys = <&pcie_phy>;
++			phy-names = "pcie-phy";
++
++			#interrupt-cells = <1>;
++			/* wild card mask, match all bus address & interrupt specifier */
++			/* format: bus address mask, interrupt specifier mask */
++			/* each bit 1 means need match, 0 means ignored when match */
++			interrupt-map-mask = <0 0 0 0>;
++			/* format: a list of: bus address, interrupt specifier,
++			 * parent interrupt controller & specifier */
++			interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
++			gpios = <&gpio1 12 0>;
++			clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
++			clock-names = "pcie", "busclk";
++			resets = <&reset RESET_PCIEA>;
++			reset-names = "pcie";
++
++			plxtech,pcie-hcsl-bit = <2>;
++			plxtech,pcie-ctrl-offset = <0x120>;
++			plxtech,pcie-outbound-offset = <0x138>;
++			status = "disabled";
++		};
++
++		pcie1: pcie-controller@47e00000 {
++			compatible = "plxtech,nas782x-pcie";
++			device_type = "pci";
++			#address-cells = <3>;
++			#size-cells = <2>;
++
++			/*		flag & space	bus address	host address	size */
++			ranges = <	0x82000000	0 0x4C000000	0x4C000000	0 0x2000000
++					0xC2000000	0 0x4E000000	0x4E000000	0 0x1E00000
++					0x81000000	0 0x4FE00000	0x4FE00000	0 0x0100000
++					0x80000000	0 0x4FF00000	0x4FF00000	0 0x0100000>;
++
++			bus-range = <0x80 0xff>;
++
++			/*	cfg			inbound translator	*/
++			reg =	<0x47e00000 0x1000>,	<0x47f00000 0x100>;
++
++			phys = <&pcie_phy>;
++			phy-names = "pcie-phy";
++
++			#interrupt-cells = <1>;
++			/* wild card mask, match all bus address & interrupt specifier */
++			/* format: bus address mask, interrupt specifier mask */
++			/* each bit 1 means need match, 0 means ignored when match */
++			interrupt-map-mask = <0 0 0 0>;
++			/* format: a list of: bus address, interrupt specifier,
++			 * parent interrupt controller & specifier */
++			interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
++
++			/* gpios = <&gpio1 12 0>; */
++			clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
++			clock-names = "pcie", "busclk";
++			resets = <&reset RESET_PCIEB>;
++			reset-names = "pcie";
++
++			plxtech,pcie-hcsl-bit = <3>;
++			plxtech,pcie-ctrl-offset = <0x124>;
++			plxtech,pcie-outbound-offset = <0x174>;
++			status = "disabled";
++		};
+ 	};
+ };