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| author | Daniel Golle <daniel@makrotopia.org> | 2021-02-18 17:59:12 +0000 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2021-02-25 16:39:55 +0000 |
| commit | 45c0e0ee419f678cf995127cef38093b974727d6 (patch) | |
| tree | e020a124176098670cb9300f53d2b0376934f20b /target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch | |
| parent | dc68af4a1312775f3aeade7c46786858725cfabe (diff) | |
| download | upstream-45c0e0ee419f678cf995127cef38093b974727d6.tar.gz upstream-45c0e0ee419f678cf995127cef38093b974727d6.tar.bz2 upstream-45c0e0ee419f678cf995127cef38093b974727d6.zip | |
oxnas: add experimental support for Linux 5.10
PCIe still reports link-down for some reason, RAID fails to assemble
despite SATA looking good (maybe a generic problem with RAID?)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch')
| -rw-r--r-- | target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch b/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch new file mode 100644 index 0000000000..e30f328792 --- /dev/null +++ b/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch @@ -0,0 +1,63 @@ +From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001 +From: Daniel Golle <daniel@makrotopia.org> +Date: Fri, 1 Jun 2018 02:41:15 +0200 +Subject: [PATCH] arm: ox820: remove left-overs + +Signed-off-by: Daniel Golle <daniel@makrotopia.org> +--- + drivers/clk/clk-oxnas.c | 2 -- + include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++------------- + 2 files changed, 14 insertions(+), 20 deletions(-) + +--- a/drivers/clk/clk-oxnas.c ++++ b/drivers/clk/clk-oxnas.c +@@ -29,8 +29,6 @@ struct oxnas_stdclk_data { + struct clk_hw_onecell_data *onecell_data; + struct clk_oxnas_gate **gates; + unsigned int ngates; +- struct clk_oxnas_pll **plls; +- unsigned int nplls; + }; + + /* Regmap offsets */ +--- a/include/dt-bindings/clock/oxsemi,ox820.h ++++ b/include/dt-bindings/clock/oxsemi,ox820.h +@@ -6,24 +6,20 @@ + #ifndef DT_CLOCK_OXSEMI_OX820_H + #define DT_CLOCK_OXSEMI_OX820_H + +-/* PLLs */ +-#define CLK_820_PLLA 0 +-#define CLK_820_PLLB 1 +- + /* Gate Clocks */ +-#define CLK_820_LEON 2 +-#define CLK_820_DMA_SGDMA 3 +-#define CLK_820_CIPHER 4 +-#define CLK_820_SD 5 +-#define CLK_820_SATA 6 +-#define CLK_820_AUDIO 7 +-#define CLK_820_USBMPH 8 +-#define CLK_820_ETHA 9 +-#define CLK_820_PCIEA 10 +-#define CLK_820_NAND 11 +-#define CLK_820_PCIEB 12 +-#define CLK_820_ETHB 13 +-#define CLK_820_REF600 14 +-#define CLK_820_USBDEV 15 ++#define CLK_820_LEON 0 ++#define CLK_820_DMA_SGDMA 1 ++#define CLK_820_CIPHER 2 ++#define CLK_820_SD 3 ++#define CLK_820_SATA 4 ++#define CLK_820_AUDIO 5 ++#define CLK_820_USBMPH 6 ++#define CLK_820_ETHA 7 ++#define CLK_820_PCIEA 8 ++#define CLK_820_NAND 9 ++#define CLK_820_PCIEB 10 ++#define CLK_820_ETHB 11 ++#define CLK_820_REF600 12 ++#define CLK_820_USBDEV 13 + + #endif /* DT_CLOCK_OXSEMI_OX820_H */ |