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authorJohn Crispin <john@openwrt.org>2014-11-26 09:00:08 +0000
committerJohn Crispin <john@openwrt.org>2014-11-26 09:00:08 +0000
commit72b58f2eb12ad4aa0c59481d0911dc5e39180eb5 (patch)
treebe51e2d36c4175443bd3ab42824df80c6b9a2efe /target/linux/oxnas/files/drivers/reset
parent40da7aae54ad7f098064f18e28eb8201afedfd5c (diff)
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add new target 'oxnas'
This is the oxnas target previously developed at http://gitorious.org/openwrt-oxnas Basically, this consolidates the changes and addtionas from http://github.org/kref/linux-oxnas into a new OpenWrt hardware target 'oxnas' adding support for PLX Technology NAS7820/NAS7821/NAS7825/... formally known as Oxford Semiconductor OXE810SE/OXE815/OX820/... For now there are 4 supported boards: Cloud Engines Pogoplug V3 (without PCIe) fully supported Cloud Engines Pogoplug Pro (with PCIe) fully supported MitraStar STG-212 aka ZyXEL NSA-212, aka Medion Akoya P89625 / P89636 / P89626 / P89630, aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587 fully supported, see http://wiki.openwrt.org/toh/medion/md86587 Shuttle KD-20 partially supported (S-ATA driver lacks support for 2nd port) Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43388
Diffstat (limited to 'target/linux/oxnas/files/drivers/reset')
-rw-r--r--target/linux/oxnas/files/drivers/reset/reset-ox820.c107
1 files changed, 107 insertions, 0 deletions
diff --git a/target/linux/oxnas/files/drivers/reset/reset-ox820.c b/target/linux/oxnas/files/drivers/reset/reset-ox820.c
new file mode 100644
index 0000000000..0a28de55f4
--- /dev/null
+++ b/target/linux/oxnas/files/drivers/reset/reset-ox820.c
@@ -0,0 +1,107 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <mach/hardware.h>
+
+static int ox820_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
+ writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
+ return 0;
+}
+
+static int ox820_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
+
+ return 0;
+}
+
+static int ox820_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
+
+ return 0;
+}
+
+static struct reset_control_ops ox820_reset_ops = {
+ .reset = ox820_reset_reset,
+ .assert = ox820_reset_assert,
+ .deassert = ox820_reset_deassert,
+};
+
+static const struct of_device_id ox820_reset_dt_ids[] = {
+ { .compatible = "plxtech,nas782x-reset", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ox820_reset_dt_ids);
+
+struct reset_controller_dev rcdev;
+
+static int ox820_reset_probe(struct platform_device *pdev)
+{
+ struct reset_controller_dev *rcdev;
+
+ rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);
+ if (!rcdev)
+ return -ENOMEM;
+
+ /* note: reset controller is statically mapped */
+
+ rcdev->owner = THIS_MODULE;
+ rcdev->nr_resets = 32;
+ rcdev->ops = &ox820_reset_ops;
+ rcdev->of_node = pdev->dev.of_node;
+ reset_controller_register(rcdev);
+ platform_set_drvdata(pdev, rcdev);
+
+ return 0;
+}
+
+static int ox820_reset_remove(struct platform_device *pdev)
+{
+ struct reset_controller_dev *rcdev = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(rcdev);
+
+ return 0;
+}
+
+static struct platform_driver ox820_reset_driver = {
+ .probe = ox820_reset_probe,
+ .remove = ox820_reset_remove,
+ .driver = {
+ .name = "ox820-reset",
+ .owner = THIS_MODULE,
+ .of_match_table = ox820_reset_dt_ids,
+ },
+};
+
+static int __init ox820_reset_init(void)
+{
+ return platform_driver_probe(&ox820_reset_driver,
+ ox820_reset_probe);
+}
+/*
+ * reset controller does not support probe deferral, so it has to be
+ * initialized before any user, in particular, PCIE uses subsys_initcall.
+ */
+arch_initcall(ox820_reset_init);
+
+MODULE_AUTHOR("Ma Haijun");
+MODULE_LICENSE("GPL");