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author | Daniel Golle <daniel@makrotopia.org> | 2019-03-10 23:04:28 +0100 |
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committer | Daniel Golle <daniel@makrotopia.org> | 2019-03-10 23:04:28 +0100 |
commit | 8ad0ba3a07b64c221db5a08523161a2cdda6194e (patch) | |
tree | 52dacd2272020347db546334e29aa9d76c00e409 /target/linux/oxnas/files/drivers/pci | |
parent | a18d41996ebfbbed0598d589e8b381d60aac802b (diff) | |
download | upstream-8ad0ba3a07b64c221db5a08523161a2cdda6194e.tar.gz upstream-8ad0ba3a07b64c221db5a08523161a2cdda6194e.tar.bz2 upstream-8ad0ba3a07b64c221db5a08523161a2cdda6194e.zip |
oxnas: move PCIe controller outside of simple-bus
Move PCIe controller outside down to SoC level to avoid resource
mapping problems.
Also add more detailed error handling when mapping registers.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/oxnas/files/drivers/pci')
-rw-r--r-- | target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c | 31 |
1 files changed, 24 insertions, 7 deletions
diff --git a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c index 68898c3beb..1dd13f9364 100644 --- a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c +++ b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c @@ -420,34 +420,51 @@ oxnas_pcie_map_registers(struct platform_device *pdev, u32 pcie_ctrl_offset; ret = of_address_to_resource(np, 0, ®s); - if (ret) + if (ret) { + dev_err(&pdev->dev, "failed to parse base register space\n"); return -EINVAL; + } + pcie->base = devm_ioremap_resource(&pdev->dev, ®s); - if (!pcie->base) + if (!pcie->base) { + dev_err(&pdev->dev, "failed to map base register space\n"); return -ENOMEM; + } ret = of_address_to_resource(np, 1, ®s); - if (ret) + if (ret) { + dev_err(&pdev->dev, "failed to parse inbound register space\n"); return -EINVAL; + } + pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s); - if (!pcie->inbound) + if (!pcie->inbound) { + dev_err(&pdev->dev, "failed to map inbound register space\n"); return -ENOMEM; + } pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL); if (IS_ERR(pcie->phy)) { - if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) + if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) { + dev_err(&pdev->dev, "failed to probe phy\n"); return PTR_ERR(pcie->phy); + } + dev_warn(&pdev->dev, "phy not attached\n"); pcie->phy = NULL; } if (of_property_read_u32(np, "plxtech,pcie-outbound-offset", - &outbound_ctrl_offset)) + &outbound_ctrl_offset)) { + dev_err(&pdev->dev, "failed to parse outbound register offset\n"); return -EINVAL; + } pcie->outbound_offset = outbound_ctrl_offset; if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset", - &pcie_ctrl_offset)) + &pcie_ctrl_offset)) { + dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n"); return -EINVAL; + } pcie->pcie_ctrl_offset = pcie_ctrl_offset; return 0; |