add 2.6.34 support

SVN-Revision: 22452

3 files changed, 138 insertions, 0 deletions

diff --git a/target/linux/octeon/patches-2.6.34/001-wndap330_hacks.patch b/target/linux/octeon/patches-2.6.34/001-wndap330_hacks.patch
new file mode 100644
index 0000000000..63f407d284
--- /dev/null
+++ b/target/linux/octeon/patches-2.6.34/001-wndap330_hacks.patch
@@ -0,0 +1,77 @@
+--- a/drivers/staging/octeon/cvmx-helper-board.c
++++ b/drivers/staging/octeon/cvmx-helper-board.c
+@@ -90,7 +90,7 @@ int cvmx_helper_board_get_mii_address(in
+ 	case CVMX_BOARD_TYPE_KODAMA:
+ 	case CVMX_BOARD_TYPE_EBH3100:
+ 	case CVMX_BOARD_TYPE_HIKARI:
+-	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
++	//case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
+ 	case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+ 	case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
+ 		/*
+@@ -103,6 +103,12 @@ int cvmx_helper_board_get_mii_address(in
+ 			return 9;
+ 		else
+ 			return -1;
++	case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
++		/* We have only one port, using GMII */
++		if (ipd_port == 0)
++			return 9;
++		else
++			return -1;
+ 	case CVMX_BOARD_TYPE_NAC38:
+ 		/* Board has 8 RGMII ports PHYs are 0-7 */
+ 		if ((ipd_port >= 0) && (ipd_port < 4))
+@@ -213,7 +219,7 @@ cvmx_helper_link_info_t __cvmx_helper_bo
+ 		result.s.speed = 1000;
+ 		return result;
+ 	case CVMX_BOARD_TYPE_EBH3100:
+-	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
++	//case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
+ 	case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+ 	case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
+ 		/* Port 1 on these boards is always Gigabit */
+@@ -225,6 +231,9 @@ cvmx_helper_link_info_t __cvmx_helper_bo
+ 		}
+ 		/* Fall through to the generic code below */
+ 		break;
++	case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
++		is_broadcom_phy = 1;
++		break;
+ 	case CVMX_BOARD_TYPE_CUST_NB5:
+ 		/* Port 1 on these boards is always Gigabit */
+ 		if (ipd_port == 1) {
+--- a/drivers/staging/octeon/cvmx-helper-rgmii.c
++++ b/drivers/staging/octeon/cvmx-helper-rgmii.c
+@@ -66,13 +66,15 @@ int __cvmx_helper_rgmii_probe(int interf
+ 			cvmx_dprintf("ERROR: RGMII initialize called in "
+ 				     "SPI interface\n");
+ 		} else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+-			   || OCTEON_IS_MODEL(OCTEON_CN30XX)
++			   //|| OCTEON_IS_MODEL(OCTEON_CN30XX)
+ 			   || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+ 			/*
+ 			 * On these chips "type" says we're in
+ 			 * GMII/MII mode. This limits us to 2 ports
+ 			 */
+ 			num_ports = 2;
++		} else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
++			num_ports = 1;
+ 		} else {
+ 			cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
+ 				     __func__);
+--- a/arch/mips/pci/pci-octeon.c
++++ b/arch/mips/pci/pci-octeon.c
+@@ -210,9 +210,11 @@ const char *octeon_get_pci_interrupts(vo
+ 		/* This is really the NAC38 */
+ 		return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
+ 	case CVMX_BOARD_TYPE_EBH3100:
+-	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
++	//case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ 	case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+ 		return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
++	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
++		return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
+ 	case CVMX_BOARD_TYPE_BBGW_REF:
+ 		return "AABCD";
+ 	case CVMX_BOARD_TYPE_THUNDER:
diff --git a/target/linux/octeon/patches-2.6.34/002-nb5_fixup.patch b/target/linux/octeon/patches-2.6.34/002-nb5_fixup.patch
new file mode 100644
index 0000000000..1d3641a73f
--- /dev/null
+++ b/target/linux/octeon/patches-2.6.34/002-nb5_fixup.patch
@@ -0,0 +1,21 @@
+--- a/arch/mips/pci/pci-octeon.c
++++ b/arch/mips/pci/pci-octeon.c
+@@ -217,6 +217,8 @@ const char *octeon_get_pci_interrupts(vo
+ 		return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
+ 	case CVMX_BOARD_TYPE_BBGW_REF:
+ 		return "AABCD";
++	case CVMX_BOARD_TYPE_CUST_NB5:
++		return "ABDABAAAAAAAAAAAAAAAAAAAAAAAAAAA";
+ 	case CVMX_BOARD_TYPE_THUNDER:
+ 	case CVMX_BOARD_TYPE_EBH3000:
+ 	default:
+--- a/drivers/staging/octeon/cvmx-helper-board.c
++++ b/drivers/staging/octeon/cvmx-helper-board.c
+@@ -707,6 +707,7 @@ cvmx_helper_board_usb_clock_types_t __cv
+ {
+ 	switch (cvmx_sysinfo_get()->board_type) {
+ 	case CVMX_BOARD_TYPE_BBGW_REF:
++	case CVMX_BOARD_TYPE_CUST_NB5:
+ 		return USB_CLOCK_TYPE_CRYSTAL_12;
+ 	}
+ 	return USB_CLOCK_TYPE_REF_48;
diff --git a/target/linux/octeon/patches-2.6.34/003-sched_clock_no_gcc44x_inline.patch b/target/linux/octeon/patches-2.6.34/003-sched_clock_no_gcc44x_inline.patch
new file mode 100644
index 0000000000..2920de260e
--- /dev/null
+++ b/target/linux/octeon/patches-2.6.34/003-sched_clock_no_gcc44x_inline.patch
@@ -0,0 +1,40 @@
+When building with a toolchain that is configured to produce 32-bits executable
+by default, we will produce __lshrti3 in sched_clock() which is never resolved
+so the kernel fails to link. Unconditionally use the inline assemble version
+as suggested by David Daney, which works around the issue.
+
+CC: David Daney <ddaney@caviumnetworks.com>
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/cavium-octeon/csrc-octeon.c |    8 --------
+ 1 files changed, 0 insertions(+), 8 deletions(-)
+
+diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
+index 0bf4bbe..36400d2 100644
+--- a/arch/mips/cavium-octeon/csrc-octeon.c
++++ b/arch/mips/cavium-octeon/csrc-octeon.c
+@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
+ unsigned long long notrace sched_clock(void)
+ {
+ 	/* 64-bit arithmatic can overflow, so use 128-bit.  */
+-#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
+ 	u64 t1, t2, t3;
+ 	unsigned long long rv;
+ 	u64 mult = clocksource_mips.mult;
+@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
+ 		: [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
+ 		: "hi", "lo");
+ 	return rv;
+-#else
+-	/* GCC > 4.3 do it the easy way.  */
+-	unsigned int __attribute__((mode(TI))) t;
+-	t = read_c0_cvmcount();
+-	t = t * clocksource_mips.mult;
+-	return (unsigned long long)(t >> clocksource_mips.shift);
+-#endif
+ }
+ 
+ void __init plat_time_init(void)
+-- 
+1.7.1
+