kernel: bump 5.4 to 5.4.150

Manually rebased:
  generic/pending-5.4/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch
  mvebu/patches-5.4/021-arm64-dts-marvell-armada-37xx-Move-PCIe-comphy-handl.patch

Removed upstreamed:
  layerscape/patches-5.4/819-uart-0004-MLK-18137-fsl_lpuart-Fix-loopback-mode.patch

All others updated automatically.

Compile-tested on: lantiq/xrx200, armvirt/64
Runtime-tested on: lantiq/xrx200, armvirt/64

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

9 files changed, 27 insertions, 27 deletions

diff --git a/target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch b/target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch
index 31f5accab6..ca10ecf6b2 100644
--- a/target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch
+++ b/target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch
@@ -33,7 +33,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
 
 --- a/drivers/pci/controller/pci-aardvark.c
 +++ b/drivers/pci/controller/pci-aardvark.c
-@@ -349,6 +349,14 @@ static void advk_pcie_setup_hw(struct ad
+@@ -353,6 +353,14 @@ static void advk_pcie_setup_hw(struct ad
  	reg |= PIO_CTRL_ADDR_WIN_DISABLE;
  	advk_writel(pcie, reg, PIO_CTRL);
  
diff --git a/target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch b/target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch
index 3ff0dcb166..d1bfd70d30 100644
--- a/target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch
+++ b/target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch
@@ -29,7 +29,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
 
 --- a/drivers/pci/controller/pci-aardvark.c
 +++ b/drivers/pci/controller/pci-aardvark.c
-@@ -311,11 +311,6 @@ static void advk_pcie_setup_hw(struct ad
+@@ -315,11 +315,6 @@ static void advk_pcie_setup_hw(struct ad
  	reg |= LANE_COUNT_1;
  	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  
@@ -41,7 +41,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  	/* Enable MSI */
  	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
  	reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
-@@ -357,7 +352,15 @@ static void advk_pcie_setup_hw(struct ad
+@@ -361,7 +356,15 @@ static void advk_pcie_setup_hw(struct ad
  	 */
  	msleep(PCI_PM_D3COLD_WAIT);
  
diff --git a/target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch b/target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch
index e3a38740c3..85ae9cabe2 100644
--- a/target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch
+++ b/target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch
@@ -42,7 +42,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  #define     PCIE_CORE_LINK_WIDTH_SHIFT				20
  #define PCIE_CORE_ERR_CAPCTL_REG				0x118
  #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX			BIT(5)
-@@ -202,6 +203,7 @@ struct advk_pcie {
+@@ -206,6 +207,7 @@ struct advk_pcie {
  	struct mutex msi_used_lock;
  	u16 msi_msg;
  	int root_bus_nr;
@@ -50,7 +50,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  	struct pci_bridge_emul bridge;
  };
  
-@@ -226,20 +228,16 @@ static int advk_pcie_link_up(struct advk
+@@ -230,20 +232,16 @@ static int advk_pcie_link_up(struct advk
  
  static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
  {
@@ -72,7 +72,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  	return -ETIMEDOUT;
  }
  
-@@ -254,6 +252,85 @@ static void advk_pcie_wait_for_retrain(s
+@@ -258,6 +256,85 @@ static void advk_pcie_wait_for_retrain(s
  	}
  }
  
@@ -158,7 +158,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  static void advk_pcie_setup_hw(struct advk_pcie *pcie)
  {
  	u32 reg;
-@@ -299,12 +376,6 @@ static void advk_pcie_setup_hw(struct ad
+@@ -303,12 +380,6 @@ static void advk_pcie_setup_hw(struct ad
  		PCIE_CORE_CTRL2_TD_ENABLE;
  	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  
@@ -171,7 +171,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  	/* Set lane X1 */
  	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  	reg &= ~LANE_CNT_MSK;
-@@ -352,20 +423,7 @@ static void advk_pcie_setup_hw(struct ad
+@@ -356,20 +427,7 @@ static void advk_pcie_setup_hw(struct ad
  	 */
  	msleep(PCI_PM_D3COLD_WAIT);
  
@@ -193,7 +193,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  
  	reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
  	reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
-@@ -1077,6 +1135,12 @@ static int advk_pcie_probe(struct platfo
+@@ -1193,6 +1251,12 @@ static int advk_pcie_probe(struct platfo
  		return ret;
  	}
  
diff --git a/target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch b/target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch
index fde01fa987..7db1c3efa5 100644
--- a/target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch
+++ b/target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch
@@ -48,7 +48,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  #include <linux/of_pci.h>
  
  #include "../pci.h"
-@@ -205,6 +207,7 @@ struct advk_pcie {
+@@ -209,6 +211,7 @@ struct advk_pcie {
  	int root_bus_nr;
  	int link_gen;
  	struct pci_bridge_emul bridge;
@@ -56,7 +56,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  };
  
  static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
-@@ -331,10 +334,31 @@ err:
+@@ -335,10 +338,31 @@ err:
  	dev_err(dev, "link never came up\n");
  }
  
@@ -88,7 +88,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  	/* Set to Direct mode */
  	reg = advk_readl(pcie, CTRL_CONFIG_REG);
  	reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
-@@ -417,7 +441,8 @@ static void advk_pcie_setup_hw(struct ad
+@@ -421,7 +445,8 @@ static void advk_pcie_setup_hw(struct ad
  
  	/*
  	 * PERST# signal could have been asserted by pinctrl subsystem before
@@ -98,7 +98,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  	 * fundamental reset. As required by PCI Express spec a delay for at
  	 * least 100ms after such a reset before link training is needed.
  	 */
-@@ -1135,6 +1160,22 @@ static int advk_pcie_probe(struct platfo
+@@ -1251,6 +1276,22 @@ static int advk_pcie_probe(struct platfo
  		return ret;
  	}
  
diff --git a/target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch b/target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch
index edff5c4a9c..0c8357d717 100644
--- a/target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch
+++ b/target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch
@@ -47,7 +47,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com>
  #include <linux/platform_device.h>
  #include <linux/of_address.h>
  #include <linux/of_gpio.h>
-@@ -103,6 +104,8 @@
+@@ -104,6 +105,8 @@
  #define     PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE	BIT(5)
  #define     PCIE_CORE_CTRL2_OB_WIN_ENABLE	BIT(6)
  #define     PCIE_CORE_CTRL2_MSI_ENABLE		BIT(10)
@@ -56,7 +56,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com>
  #define PCIE_MSG_LOG_REG			(CONTROL_BASE_ADDR + 0x30)
  #define PCIE_ISR0_REG				(CONTROL_BASE_ADDR + 0x40)
  #define PCIE_MSG_PM_PME_MASK			BIT(7)
-@@ -208,6 +211,7 @@ struct advk_pcie {
+@@ -212,6 +215,7 @@ struct advk_pcie {
  	int link_gen;
  	struct pci_bridge_emul bridge;
  	struct gpio_desc *reset_gpio;
@@ -64,7 +64,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com>
  };
  
  static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
-@@ -359,6 +363,11 @@ static void advk_pcie_setup_hw(struct ad
+@@ -363,6 +367,11 @@ static void advk_pcie_setup_hw(struct ad
  
  	advk_pcie_issue_perst(pcie);
  
@@ -76,7 +76,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com>
  	/* Set to Direct mode */
  	reg = advk_readl(pcie, CTRL_CONFIG_REG);
  	reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
-@@ -1125,6 +1134,62 @@ out_release_res:
+@@ -1241,6 +1250,62 @@ out_release_res:
  	return err;
  }
  
@@ -139,7 +139,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com>
  static int advk_pcie_probe(struct platform_device *pdev)
  {
  	struct device *dev = &pdev->dev;
-@@ -1182,6 +1247,10 @@ static int advk_pcie_probe(struct platfo
+@@ -1298,6 +1363,10 @@ static int advk_pcie_probe(struct platfo
  	else
  		pcie->link_gen = ret;
  
diff --git a/target/linux/mvebu/patches-5.4/021-arm64-dts-marvell-armada-37xx-Move-PCIe-comphy-handl.patch b/target/linux/mvebu/patches-5.4/021-arm64-dts-marvell-armada-37xx-Move-PCIe-comphy-handl.patch
index b851a39a39..9c71225ffe 100644
--- a/target/linux/mvebu/patches-5.4/021-arm64-dts-marvell-armada-37xx-Move-PCIe-comphy-handl.patch
+++ b/target/linux/mvebu/patches-5.4/021-arm64-dts-marvell-armada-37xx-Move-PCIe-comphy-handl.patch
@@ -42,12 +42,12 @@ Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
  	max-link-speed = <2>;
  	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
 -	phys = <&comphy1 0>;
- 
- 	/* enabled by U-Boot if PCIe module is present */
- 	status = "disabled";
+ 	/*
+ 	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
+ 	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
 +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
-@@ -494,6 +494,7 @@
+@@ -501,6 +501,7 @@
  					<0 0 0 2 &pcie_intc 1>,
  					<0 0 0 3 &pcie_intc 2>,
  					<0 0 0 4 &pcie_intc 3>;
diff --git a/target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch b/target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch
index 4442a5ac15..47176e4893 100644
--- a/target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch
+++ b/target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch
@@ -30,11 +30,11 @@ Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
  	status = "okay";
 -	max-link-speed = <2>;
  	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
- 
- 	/* enabled by U-Boot if PCIe module is present */
+ 	/*
+ 	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
 +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
-@@ -494,6 +494,7 @@
+@@ -501,6 +501,7 @@
  					<0 0 0 2 &pcie_intc 1>,
  					<0 0 0 3 &pcie_intc 2>,
  					<0 0 0 4 &pcie_intc 3>;
diff --git a/target/linux/mvebu/patches-5.4/024-PCI-aardvark-Don-t-touch-PCIe-registers-if-no-card-c.patch b/target/linux/mvebu/patches-5.4/024-PCI-aardvark-Don-t-touch-PCIe-registers-if-no-card-c.patch
index 04803c90d8..f38b6b56bb 100644
--- a/target/linux/mvebu/patches-5.4/024-PCI-aardvark-Don-t-touch-PCIe-registers-if-no-card-c.patch
+++ b/target/linux/mvebu/patches-5.4/024-PCI-aardvark-Don-t-touch-PCIe-registers-if-no-card-c.patch
@@ -34,7 +34,7 @@ Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
 
 --- a/drivers/pci/controller/pci-aardvark.c
 +++ b/drivers/pci/controller/pci-aardvark.c
-@@ -650,6 +650,13 @@ static bool advk_pcie_valid_device(struc
+@@ -725,6 +725,13 @@ static bool advk_pcie_valid_device(struc
  	if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
  		return false;
  
diff --git a/target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch b/target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch
index ff67c9c02f..117f9b3576 100644
--- a/target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch
+++ b/target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch
@@ -31,7 +31,7 @@ Cc: <stable@vger.kernel.org> # 5.8+: ea17a0f153af: phy: marvell: comphy: Convert
 
 --- a/drivers/pci/controller/pci-aardvark.c
 +++ b/drivers/pci/controller/pci-aardvark.c
-@@ -1165,7 +1165,9 @@ static int advk_pcie_enable_phy(struct a
+@@ -1281,7 +1281,9 @@ static int advk_pcie_enable_phy(struct a
  	}
  
  	ret = phy_power_on(pcie->phy);