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authorHauke Mehrtens <hauke@hauke-m.de>2021-10-02 15:28:55 +0200
committerHauke Mehrtens <hauke@hauke-m.de>2021-10-02 16:45:56 +0200
commit50f456b46cbae27ed13badfe7b2976cd01b67a57 (patch)
tree9911069e0538585942fe2c16685e7ed3afbff674 /target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch
parent78cf3e53b1f4ea6428925302d78f743a693d5fb1 (diff)
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kernel: bump 5.4 to 5.4.150
Manually rebased: generic/pending-5.4/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch mvebu/patches-5.4/021-arm64-dts-marvell-armada-37xx-Move-PCIe-comphy-handl.patch Removed upstreamed: layerscape/patches-5.4/819-uart-0004-MLK-18137-fsl_lpuart-Fix-loopback-mode.patch All others updated automatically. Compile-tested on: lantiq/xrx200, armvirt/64 Runtime-tested on: lantiq/xrx200, armvirt/64 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch')
-rw-r--r--target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch6
1 files changed, 3 insertions, 3 deletions
diff --git a/target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch b/target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch
index 4442a5ac15..47176e4893 100644
--- a/target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch
+++ b/target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch
@@ -30,11 +30,11 @@ Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
status = "okay";
- max-link-speed = <2>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
-
- /* enabled by U-Boot if PCIe module is present */
+ /*
+ * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
-@@ -494,6 +494,7 @@
+@@ -501,6 +501,7 @@
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;