mvebu: backport CN9130 dts necessary files changes to 5.4

 1. Add support for Marvell CN9130 SoC
 2. Add support for CP115,and create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115
 3. Add support for AP807/AP807-quad,AP807 is a major component of CN9130 SoC series
 4. Drop PCIe I/O ranges from CP11x file and externalize PCIe macros from CP11x file

Signed-off-by: Ian Chang <ianchang@ieiworld.com>

1 files changed, 129 insertions, 0 deletions

diff --git a/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch b/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch
new file mode 100644
index 0000000000..0dd9e8f90f
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch
@@ -0,0 +1,129 @@
+From 5f07b26e85dc86f017833ea745ff4e5b420280cd Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:31 +0200
+Subject: [PATCH] arm64: dts: marvell: Externalize PCIe macros from CP11x file
+
+PCIe macros are specific to CP110 and will not fit CP115
+constraints. To keep the same way the files are organized, just move
+some macros out of the CP11x generic file and define them directly in
+SoC DTSI, instead of defining single addresses in the SoC DTSI and
+reusing them in macros.
+
+In the end:
+* CP11X_PCIE_MEM_BASE SoC define is dropped
+* CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the
+  SoC files as it replaces the above definition.
+* As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with
+  newer SoCs, we put it in the SoC files as well.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-70x0.dtsi  |  6 ++++--
+ arch/arm64/boot/dts/marvell/armada-80x0.dtsi  | 12 ++++++++----
+ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi |  9 ++++-----
+ 3 files changed, 16 insertions(+), 11 deletions(-)
+
+--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+@@ -19,7 +19,8 @@
+  */
+ #define CP11X_NAME		cp0
+ #define CP11X_BASE		f2000000
+-#define CP11X_PCIE_MEM_BASE	0xf6000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE	f2600000
+ #define CP11X_PCIE1_BASE	f2620000
+ #define CP11X_PCIE2_BASE	f2640000
+@@ -28,7 +29,8 @@
+ 
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+@@ -21,7 +21,8 @@
+  */
+ #define CP11X_NAME		cp0
+ #define CP11X_BASE		f2000000
+-#define CP11X_PCIE_MEM_BASE	0xf6000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE	f2600000
+ #define CP11X_PCIE1_BASE	f2620000
+ #define CP11X_PCIE2_BASE	f2640000
+@@ -30,7 +31,8 @@
+ 
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+@@ -40,7 +42,8 @@
+  */
+ #define CP11X_NAME		cp1
+ #define CP11X_BASE		f4000000
+-#define CP11X_PCIE_MEM_BASE	0xfa000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE	f4600000
+ #define CP11X_PCIE1_BASE	f4620000
+ #define CP11X_PCIE2_BASE	f4640000
+@@ -49,7 +52,8 @@
+ 
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+@@ -10,8 +10,7 @@
+ 
+ #include "armada-common.dtsi"
+ 
+-#define CP11X_PCIEx_MEM_BASE(iface)	(CP11X_PCIE_MEM_BASE + (iface *  0x1000000))
+-#define CP11X_PCIEx_CONF_BASE(iface)	(CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
++#define CP11X_PCIEx_CONF_BASE(iface)	(CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
+ 
+ / {
+ 	/*
+@@ -507,7 +506,7 @@
+ 
+ 		bus-range = <0 0xff>;
+ 		/* non-prefetchable memory */
+-		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0  CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
++		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0  CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
+ 		interrupt-map-mask = <0 0 0 0>;
+ 		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+@@ -531,7 +530,7 @@
+ 
+ 		bus-range = <0 0xff>;
+ 		/* non-prefetchable memory */
+-		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0  CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
++		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0  CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
+ 		interrupt-map-mask = <0 0 0 0>;
+ 		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+@@ -556,7 +555,7 @@
+ 
+ 		bus-range = <0 0xff>;
+ 		/* non-prefetchable memory */
+-		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0  CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
++		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0  CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
+ 		interrupt-map-mask = <0 0 0 0>;
+ 		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;