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authorScott Roberts <ttocsr@gmail.com>2019-09-27 14:19:01 -0600
committerHauke Mehrtens <hauke@hauke-m.de>2019-10-12 23:43:08 +0200
commitd2a1075973728b55231688809b68a0f0b93c9da4 (patch)
treeaa026543b3be26f0e5b71c4596f9e7a4b440e486 /target/linux/mvebu/patches-4.19/538-phy-add-QSGMII-and-PCIE-modes.patch
parente11fc8439c9f7230441408c4d257efc46f372312 (diff)
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mvebu: backport mvneta and comphy from linux 5.x
These patches backport support for the ARMADA 3700 COMPHY driver. Also backported is the mvneta driver. This will allow switching the SGMII speed using SMC calls. To support this you must update the firmware using Marvells 18.12 version (this has now been upstreamed). The mvneta driver allows 2500basex and 2500baset. Signed-off-by: Scott Roberts <ttocsr@gmail.com>
Diffstat (limited to 'target/linux/mvebu/patches-4.19/538-phy-add-QSGMII-and-PCIE-modes.patch')
-rw-r--r--target/linux/mvebu/patches-4.19/538-phy-add-QSGMII-and-PCIE-modes.patch28
1 files changed, 28 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-4.19/538-phy-add-QSGMII-and-PCIE-modes.patch b/target/linux/mvebu/patches-4.19/538-phy-add-QSGMII-and-PCIE-modes.patch
new file mode 100644
index 0000000000..b759b9fb25
--- /dev/null
+++ b/target/linux/mvebu/patches-4.19/538-phy-add-QSGMII-and-PCIE-modes.patch
@@ -0,0 +1,28 @@
+From c2a90025ad09d830c8d8ae69f485eac6aaaa2472 Mon Sep 17 00:00:00 2001
+From: Quentin Schulz <quentin.schulz@bootlin.com>
+Date: Thu, 4 Oct 2018 14:22:03 +0200
+Subject: [PATCH] phy: add QSGMII and PCIE modes
+
+Prepare for upcoming phys that'll handle QSGMII or PCIe.
+
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ include/linux/phy/phy.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/phy/phy.h
++++ b/include/linux/phy/phy.h
+@@ -37,9 +37,11 @@ enum phy_mode {
+ PHY_MODE_USB_OTG,
+ PHY_MODE_SGMII,
+ PHY_MODE_2500SGMII,
++ PHY_MODE_QSGMII,
+ PHY_MODE_10GKR,
+ PHY_MODE_UFS_HS_A,
+ PHY_MODE_UFS_HS_B,
++ PHY_MODE_PCIE,
+ };
+
+ /**