mvebu: backport mainline patches from kernel 3.13

This is a backport of the patches accepted to the Linux mainline related to
mvebu SoC (Armada XP and Armada 370) between Linux v3.12, and Linux v3.13.
This work mainly covers:

* Finishes work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c)
  between the PXA family, and the Armada family.
* timer initialization update, and access function for the Armada family.
* Generic IRQ handling backporting.
* Some bug fixes.

Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com>
CC: Luka Perkov <luka@openwrt.org>

SVN-Revision: 39566

1 files changed, 62 insertions, 0 deletions

diff --git a/target/linux/mvebu/patches-3.10/0175-ARM-mvebu-Relocate-PCIe-node-in-Armada-370-RD-board.patch b/target/linux/mvebu/patches-3.10/0175-ARM-mvebu-Relocate-PCIe-node-in-Armada-370-RD-board.patch
new file mode 100644
index 0000000000..3b37ab93e6
--- /dev/null
+++ b/target/linux/mvebu/patches-3.10/0175-ARM-mvebu-Relocate-PCIe-node-in-Armada-370-RD-board.patch
@@ -0,0 +1,62 @@
+From 079d1ecae4bd4166a0f89bcb8e0c96bec1b39622 Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
+Date: Thu, 8 Aug 2013 18:03:09 -0300
+Subject: [PATCH 175/203] ARM: mvebu: Relocate PCIe node in Armada 370 RD board
+
+The pcie-controller node needs to be relocated according the MBus
+DT binding, since it's now a child of the mbus-compatible node.
+
+Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+---
+ arch/arm/boot/dts/armada-370-rd.dts | 32 ++++++++++++++++----------------
+ 1 file changed, 16 insertions(+), 16 deletions(-)
+
+--- a/arch/arm/boot/dts/armada-370-rd.dts
++++ b/arch/arm/boot/dts/armada-370-rd.dts
+@@ -31,6 +31,22 @@
+ 		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ 			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+ 
++		pcie-controller {
++			status = "okay";
++
++			/* Internal mini-PCIe connector */
++			pcie@1,0 {
++				/* Port 0, Lane 0 */
++				status = "okay";
++			};
++
++			/* Internal mini-PCIe connector */
++			pcie@2,0 {
++				/* Port 1, Lane 0 */
++				status = "okay";
++			};
++		};
++
+ 		internal-regs {
+ 			serial@12000 {
+ 				clock-frequency = <200000000>;
+@@ -88,22 +104,6 @@
+ 					gpios = <&gpio0 6 1>;
+ 				};
+ 			};
+-
+-			pcie-controller {
+-				status = "okay";
+-
+-				/* Internal mini-PCIe connector */
+-				pcie@1,0 {
+-					/* Port 0, Lane 0 */
+-					status = "okay";
+-				};
+-
+-				/* Internal mini-PCIe connector */
+-				pcie@2,0 {
+-					/* Port 1, Lane 0 */
+-					status = "okay";
+-				};
+-			};
+ 		};
+ 	};
+  };