mvebu: backport mainline patches from kernel 3.12

This is a backport of the patches accepted to the Linux mainline related to
mvebu SoC (Armada XP and Armada 370) between Linux v3.11, and Linux v3.12.
This work mainly covers:

* Ground work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c)
  between the PXA family,and the Armada family.
* Further updates to the mvebu MBus.
* Work and ground work for enabling MSI on the Armada family.
* some phy / mdio bus initialization related work.
* Device tree binding documentation update.

Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com>
CC: Luka Perkov <luka@openwrt.org>

SVN-Revision: 39565

1 files changed, 44 insertions, 0 deletions

diff --git a/target/linux/mvebu/patches-3.10/0086-irqchip-armada-370-xp-fix-MSI-race-condition.patch b/target/linux/mvebu/patches-3.10/0086-irqchip-armada-370-xp-fix-MSI-race-condition.patch
new file mode 100644
index 0000000000..ebbc532391
--- /dev/null
+++ b/target/linux/mvebu/patches-3.10/0086-irqchip-armada-370-xp-fix-MSI-race-condition.patch
@@ -0,0 +1,44 @@
+From ddda6fa410b6e50ee67d4a628187e76b4a6c9b28 Mon Sep 17 00:00:00 2001
+From: Lior Amsalem <alior@marvell.com>
+Date: Mon, 25 Nov 2013 17:26:45 +0100
+Subject: [PATCH 086/203] irqchip: armada-370-xp: fix MSI race condition
+
+In the Armada 370/XP driver, when we receive an IRQ 1, we read the
+list of doorbells that caused the interrupt from register
+ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS. This gives the list of MSIs that
+were generated. However, instead of acknowledging only the MSIs that
+were generated, we acknowledge *all* the MSIs, by writing
+~MSI_DOORBELL_MASK in the ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS register.
+
+This creates a race condition: if a new MSI that isn't part of the
+ones read into the temporary "msimask" variable is fired before we
+acknowledge all MSIs, then we will simply loose it.
+
+It is important to mention that this ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
+register has the following behavior: "A CPU write of 0 clears the bits
+in this field. A CPU write of 1 has no effect". This is what allows us
+to simply write ~msimask to acknoledge the handled MSIs.
+
+Notice that the same problem is present in the IPI implementation, but
+it is fixed as a separate patch, so that this IPI fix can be pushed to
+older stable versions as appropriate (all the way to 3.8), while the
+MSI code only appeared in 3.13.
+
+Signed-off-by: Lior Amsalem <alior@marvell.com>
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+---
+ drivers/irqchip/irq-armada-370-xp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/irqchip/irq-armada-370-xp.c
++++ b/drivers/irqchip/irq-armada-370-xp.c
+@@ -381,7 +381,7 @@ armada_370_xp_handle_irq(struct pt_regs
+ 						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
+ 				& PCI_MSI_DOORBELL_MASK;
+ 
+-			writel(~PCI_MSI_DOORBELL_MASK, per_cpu_int_base +
++			writel(~msimask, per_cpu_int_base +
+ 			       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+ 
+ 			for (msinr = PCI_MSI_DOORBELL_START;