mvebu: backport mainline patches from kernel 3.12

This is a backport of the patches accepted to the Linux mainline related to
mvebu SoC (Armada XP and Armada 370) between Linux v3.11, and Linux v3.12.
This work mainly covers:

* Ground work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c)
  between the PXA family,and the Armada family.
* Further updates to the mvebu MBus.
* Work and ground work for enabling MSI on the Armada family.
* some phy / mdio bus initialization related work.
* Device tree binding documentation update.

Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com>
CC: Luka Perkov <luka@openwrt.org>

SVN-Revision: 39565

1 files changed, 67 insertions, 0 deletions

diff --git a/target/linux/mvebu/patches-3.10/0053-ARM-mvebu-Remove-the-harcoded-BootROM-window-allocat.patch b/target/linux/mvebu/patches-3.10/0053-ARM-mvebu-Remove-the-harcoded-BootROM-window-allocat.patch
new file mode 100644
index 0000000000..393bfc32c6
--- /dev/null
+++ b/target/linux/mvebu/patches-3.10/0053-ARM-mvebu-Remove-the-harcoded-BootROM-window-allocat.patch
@@ -0,0 +1,67 @@
+From 23a9b291a7b9ba28b31da56e6ced7a8168baa3de Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
+Date: Tue, 21 May 2013 11:01:33 -0300
+Subject: [PATCH 053/203] ARM: mvebu: Remove the harcoded BootROM window
+ allocation
+
+The address decoding window to access the BootROM should not be
+allocated programatically, but instead declared in the device tree.
+
+Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
+Tested-by: Andrew Lunn <andrew@lunn.ch>
+Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ arch/arm/mach-mvebu/platsmp.c | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/mach-mvebu/platsmp.c
++++ b/arch/arm/mach-mvebu/platsmp.c
+@@ -21,6 +21,7 @@
+ #include <linux/smp.h>
+ #include <linux/clk.h>
+ #include <linux/of.h>
++#include <linux/of_address.h>
+ #include <linux/mbus.h>
+ #include <asm/cacheflush.h>
+ #include <asm/smp_plat.h>
+@@ -29,6 +30,9 @@
+ #include "pmsu.h"
+ #include "coherency.h"
+ 
++#define AXP_BOOTROM_BASE 0xfff00000
++#define AXP_BOOTROM_SIZE 0x100000
++
+ void __init set_secondary_cpus_clock(void)
+ {
+ 	int thiscpu;
+@@ -115,10 +119,29 @@ static void __init armada_xp_smp_init_cp
+ 
+ void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
+ {
++	struct device_node *node;
++	struct resource res;
++	int err;
++
+ 	set_secondary_cpus_clock();
+ 	flush_cache_all();
+ 	set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+-	mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
++
++	/*
++	 * In order to boot the secondary CPUs we need to ensure
++	 * the bootROM is mapped at the correct address.
++	 */
++	node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
++	if (!node)
++		panic("Cannot find 'marvell,bootrom' compatible node");
++
++	err = of_address_to_resource(node, 0, &res);
++	if (err < 0)
++		panic("Cannot get 'bootrom' node address");
++
++	if (res.start != AXP_BOOTROM_BASE ||
++	    resource_size(&res) != AXP_BOOTROM_SIZE)
++		panic("The address for the BootROM is incorrect");
+ }
+ 
+ struct smp_operations armada_xp_smp_ops __initdata = {