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author | Imre Kaloz <kaloz@openwrt.org> | 2014-06-17 15:13:10 +0000 |
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committer | Imre Kaloz <kaloz@openwrt.org> | 2014-06-17 15:13:10 +0000 |
commit | d775e4ef00e08c839a41e101552be171ff638d3d (patch) | |
tree | 4024679a777f738166057959372d0706830fcd7e /target/linux/mvebu/files/arch | |
parent | 099d998fcf21c80e25a9518607285d1437d89be9 (diff) | |
download | upstream-d775e4ef00e08c839a41e101552be171ff638d3d.tar.gz upstream-d775e4ef00e08c839a41e101552be171ff638d3d.tar.bz2 upstream-d775e4ef00e08c839a41e101552be171ff638d3d.zip |
preliminary support for the WRT1900AC (work in progress)
SVN-Revision: 41232
Diffstat (limited to 'target/linux/mvebu/files/arch')
-rw-r--r-- | target/linux/mvebu/files/arch/arm/boot/dts/armada-xp-mamba.dts | 242 |
1 files changed, 242 insertions, 0 deletions
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-xp-mamba.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-xp-mamba.dts new file mode 100644 index 0000000000..d732764e90 --- /dev/null +++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-xp-mamba.dts @@ -0,0 +1,242 @@ +/* + * Device Tree file for the Linksys WRT1900AC (Mamba). + * + * Note: this board is shipped with a new generation boot loader that + * remaps internal registers at 0xf1000000. Therefore, if earlyprintk + * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be + * used. + * + * Copyright (C) 2013 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Linksys WRT1900AC (Mamba)"; + compatible = "linksys,mamba", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* Etron EJ168 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* First mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + }; + + internal-regs { + pinctrl { + pinctrl-0 = <&pmx_phy_int>; + pinctrl-names = "default"; + + pmx_ge0: pmx-ge0 { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11"; + marvell,function = "ge0"; + }; + + pmx_ge1: pmx-ge1 { + marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge1"; + }; + + pmx_keys: pmx-keys { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + pmx_spi: pmx-spi { + marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; + marvell,function = "spi"; + }; + + pmx_phy_int: pmx-phy-int { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + clock-frequency = <250000000>; + status = "okay"; + }; + + serial@12100 { + clock-frequency = <250000000>; + status = "okay"; + }; + + sata@a0000 { + nr-ports = <1>; + status = "okay"; + }; + + mdio { + disabled; + }; + + ethernet@70000 { + pinctrl-0 = <&pmx_ge0>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@74000 { + pinctrl-0 = <&pmx_ge1>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + /* USB part of the eSATA/USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + tlc59116@68 { + #gpio-cells = <2>; + compatible = "gpio,tlc59116"; + reg = <0x68>; + gpio-controller; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; /* 1MB */ + read-only; + }; + + partition@100000 { + label = "u_env"; //u-boot-env? + reg = <0x100000 0x40000>; /* 256KB */ + read-only; + }; + + partition@140000 { + label = "s_env"; + reg = <0x140000 0x40000>; /* 256KB */ + read-only; + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MB */ + }; + + partition@a00000 { + label = "kernel"; + reg = <0xa00000 0x2800000>; /* 40MB */ + }; + + partition@d00000 { + label = "rootfs"; + reg = <0xd00000 0x2500000>; /* 37MB */ + }; + + partition@3200000 { + label = "alt_kernel"; + reg = <0x3200000 0x2800000>; /* 40MB */ + }; + + partition@3500000 { + label = "alt_rootfs"; + reg = <0x3500000 0x2500000>; /* 37MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; /* ?MB */ + }; + }; + + spi0: spi@10600 { + status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mr25h256"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_keys>; + pinctrl-names = "default"; + + button@1 { + label = "Factory Reset Button"; + linux,code = <141>; /* KEY_SETUP */ + gpios = <&gpio1 1 1>; + }; + }; +}; |