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| author | Tomasz Maciej Nowak <tomek_n@o2.pl> | 2020-03-18 19:04:12 +0100 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2020-03-28 22:58:36 +0100 |
| commit | 2d61f8821c7cf99354e904139226c132554ba180 (patch) | |
| tree | 78725e38a3d91e0d65f3cc7ad2e31ee33aa1fd5c /target/linux/mvebu/cortexa9 | |
| parent | 43d1d88510621801d66a0a7f46f4c4f44d89633a (diff) | |
| download | upstream-2d61f8821c7cf99354e904139226c132554ba180.tar.gz upstream-2d61f8821c7cf99354e904139226c132554ba180.tar.bz2 upstream-2d61f8821c7cf99354e904139226c132554ba180.zip | |
mvebu: cortexa9: correct cpu subtype
Armada 370 processors have only 16 double-precision registers. The
change introduced by 8dcc1087602e ("toolchain: ARM: Fix toolchain
compilation for gcc 8.x") switched accidentally the toolchain for mvebu
cortexa9 subtarget to cpu type with 32 double-precision registers. This
stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu
is specified. That change resulted in unusable image, in which kernel
will kill userspace as soon as it causing "Illegal instruction".
Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272
Fixes: 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for
gcc 8.x")
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
Diffstat (limited to 'target/linux/mvebu/cortexa9')
| -rw-r--r-- | target/linux/mvebu/cortexa9/target.mk | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/mvebu/cortexa9/target.mk b/target/linux/mvebu/cortexa9/target.mk index 2a75599bc9..cdd4d86e49 100644 --- a/target/linux/mvebu/cortexa9/target.mk +++ b/target/linux/mvebu/cortexa9/target.mk @@ -10,5 +10,5 @@ include $(TOPDIR)/rules.mk ARCH:=arm BOARDNAME:=Marvell Armada 37x/38x/XP CPU_TYPE:=cortex-a9 -CPU_SUBTYPE:=vfpv3 +CPU_SUBTYPE:=vfpv3-d16 KERNELNAME:=zImage dtbs |