mpc85xx: add support for Extreme Networks WS-AP3825i

Hardware:

- SoC:     Freescale P1020
  - CPU:     2x e500v2 @ 800MHz
- Flash:   64MiB NOR (1x Intel JS28F512)
- Memory:  256MiB (2x ProMOS DDR3 V73CAG01168RBJ-I9H 1Gb)
- WiFi1:   2.4+5GHz abgn 3x3 (Atheros AR9590)
- Wifi2:   5GHz an+ac 3x3 (Qualcomm Atheros QCA9890)
- ETH:     2x PoE Gigabit Ethernet (2x Atheros AR8035)
- Power:   12V (center-positive barrel) or 48V PoE (active or passive)
- Serial:  Cisco-compatible RJ45 next to 12V power socket (115200 baud)
- LED Driver: TI LV164A
  - LEDs: (not functioning)
    - 2x Power (Green + Orange)
    - 4x ETH (ETH1 + ETH2) x (Green + Orange)
    - 2x WiFi (WiFi2 + WiFi1)

Installation:

1. Grab the OpenWrt initramfs <openwrt-initramfs-bin>, e.g.
   openwrt-mpc85xx-p1020-extreme-networks_ws-ap3825i-initramfs-kernel.bin.
   Place it in the root directory of a DHCP+TFTP server, e.g. OpenWrt
   `dnsmasq` with configuration `dhcp.server.enable_tftp='1'`.

2. Connect to the serial port and boot the AP with options
   e.g. 115200,N,8. Stop autoboot in U-Boot by pressing Enter after
   'Scanning JFFS2 FS:' begins, then waiting for the prompt to be
   interrupted. Credentials are identical to the one in the APs
   interface. By default it is admin / new2day: if these do not work,
   follow the OEM's reset procedure using the reset button.

3. Set the bootcmd so the AP can boot OpenWrt by executing:

```uboot
setenv boot_openwrt "cp.b 0xEC000000 0x2000000 0x2000000; interrupts off; bootm start 0x2000000; bootm loados; fdt resize; fdt boardsetup; fdt chosen; bootm prep; bootm go;"
setenv bootcmd "run boot_openwrt"
saveenv
```

   If you plan on going back to the vendor firmware - the bootcmd for it
   is stored in the boot_flash variable.

4. Load the initramfs image to RAM and boot by executing

```uboot
setenv ipaddr <ipv4 client address>;
setenv serverip <tftp server address>;
tftpboot 0x2000000 <openwrt-initramfs-bin>;
interrupts off;
bootm start 0x2000000;
bootm loados;
fdt resize;
fdt boardsetup;
fdt chosen;
bootm prep;
bootm go;
```

5. Make a backup of the "firmware" partition if you ever wish to go back
   to the vendor firmware.

6. Upload the OpenWrt sysupgrade image via SCP to the devices /tmp
   folder.

7. Flash OpenWrt using sysupgrade.

```ash
sysupgrade /tmp/<openwrt-sysupgrade-bin>
```

Notes:

- We must step through the `bootm` process manually to avoid fdt
  relocation. To explain: the stock U-boot (and stock Linux) are configured
  with a very large CONFIG_SYS_BOOTMAPSZ (and the device's stock Linux
  kernel is configured to be able to handle it). The U-boot version
  predates the check for the `fdt_high` variable, meaning that upon fdt
  relocation, the fdt can (and will) be moved to a very high address; the
  default appears to be 0x9ffa000. This address is so high that when the
  Linux kernel starts reading the fdt at the beginning of the boot process,
  it encounters a memory access exception and panics[5]. While it is
  possible to reduce the highest address the fdt will be relocated to by
  setting `bootm_size`, this also has the side effect of limiting the
  amount of RAM the kernel can use[3].

- Because it is not relocated, the flattened device tree needs to be
  padded in the build process to guarantee that `fdt resize` has
  enough space.

- The primary ethernet MAC address is stored (and set) in U-boot; they are
  shimmed into the device tree by 'fdt boardsetup' through the
  'local-mac-address' property of the respective ethernet node, so OpenWrt
  does not need to set this at runtime. Note that U-boot indexes the
  ethernet nodes by alias, which is why the device tree explicitly aliases
  ethernet1 to enet2.

- LEDs do not function under OpenWrt. Each of 8 LEDs is connected to an
  output of a TI LV164A shift register, which is wired to GPIO lines and
  operates through bit-banged SPI. Unfortunately, I am unable to get the
  spi-gpio driver to recognize the `led_spi` device tree node at all, as
  confirmed by patching in printk messages demonstrating
  spi-gpio.c::spi_gpio_probe never runs. It is possible to manually
  articulate the shift register by exporting the GPIO lines and stepping
  their values through the sysfs.

- Though they do not function under OpenWrt, I have left the pinout details
  of the LEDs and shift register in the device tree to represent real
  hardware.

- An archive of the u-boot and Linux source for the AP3825i (which is one
  device of a range of devices code-named 'CHANTRY') be found here[1].

- The device has an identical case to both the Enterasys WS-AP3725i and
  Adtran BSAP-2030[2] (and potentially other Adtran BSAPs). Given that
  there is no FCC ID for the board itself (only its WLAN modules), it's
  likely these are generic boards, and even that the WS-AP3725i is
  identical, with only a change in WLAN card. I have ordered one to confirm
  this.

- For additional information: the process of porting the board is
  documented in an OpenWrt forum thread[4].

[1]: magnet:?xt=urn:btih:f5306a5dfd06d42319e4554565429f84dde96bbc
[2]: https://forum.openwrt.org/t/support-for-adtran-bluesocket-bsap-2030/48538
[3]: https://forum.openwrt.org/t/adding-openwrt-support-for-ws-ap3825i/101168/29
[4]: https://forum.openwrt.org/t/adding-openwrt-support-for-ws-ap3825i/101168
[5]: https://forum.openwrt.org/t/adding-openwrt-support-for-ws-ap3825i/101168/26

Tested-by: Martin Kennedy <hurricos@gmail.com>
Signed-off-by: Martin Kennedy <hurricos@gmail.com>

2 files changed, 340 insertions, 0 deletions

diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts
new file mode 100644
index 0000000000..3dcbac21a4
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+/include/ "fsl/p1020si-pre.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Extreme Networks WS-AP3825i";
+	compatible = "extreme-networks,ws-ap3825i";
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet2;
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+	};
+
+	chosen {
+		bootargs-override = "console=ttyS0,115200";
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	led_spi {
+		/* 
+		 * This is currently non-functioning because the spi-gpio
+		 * driver refuses to register when presented with this node.
+		 */
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <0>;
+
+		spi_gpio: led_gpio@0 {
+			compatible = "fairchild,74hc595";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			registers-number = <1>;
+			spi-max-frequency = <100000>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wifi1 {
+			gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3825i:green:radio1";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		wifi2 {
+			gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3825i:green:radio2";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_power_green: power_green {
+			gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3825i:green:power";
+		};
+
+		led_power_red: power_red {
+			gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3825i:red:power";
+		};
+
+		eth0_red {
+			gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3825i:red:eth0";
+		};
+
+		eth0_green {
+			gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3825i:green:eth0";
+		};
+
+		eth1_red {
+			gpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3825i:red:eth1";
+		};
+
+		eth1_green {
+			gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3825i:green:eth1";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					compatible = "denx,fit";
+					reg = <0x0 0x3d60000>;
+					label = "firmware";
+				};
+
+				partition@3d60000 {
+					reg = <0x3d60000 0x20000>;
+					label = "calib";
+					read-only;
+				};
+
+				partition@3d80000{
+					reg = <0x3d80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@3e00000{
+					reg = <0x3e00000 0x100000>;
+					label = "nvram";
+					read-only;
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "cfg2";
+					read-only;
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "cfg1";
+					read-only;
+				};
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				interrupts = <3 1 0 0>;
+				reg = <0x5>;
+				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+			};
+
+			phy2: ethernet-phy@2 {
+				interrupts = <1 1 0 0>;
+				reg = <0x6>;
+				reset-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			status = "okay";
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "okay";
+			phy-handle = <&phy2>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/ws-ap3825i.c b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/ws-ap3825i.c
new file mode 100644
index 0000000000..5a0919c200
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/ws-ap3825i.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Extreme Networks WS-AP3825i Board Setup
+ *
+ * Copyright (C) 2021 Martin Kennedy <hurricos@gmail.com>
+ *
+ * Based on:
+ *   mpc85xx_rdb.c:
+ *      MPC85xx RDB Board Setup
+ *      Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init ws_ap3825i_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init ws_ap3825i_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("ws_ap3825i_setup_arch()", 0);
+
+	mpc85xx_smp_init();
+
+	fsl_pci_assign_primary();
+
+	pr_info("WS-AP3825i board from Extreme Networks\n");
+}
+
+machine_arch_initcall(ws_ap3825i, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ws_ap3825i_probe(void)
+{
+	if (of_machine_is_compatible("extreme-networks,ws-ap3825i"))
+		return 1;
+	return 0;
+}
+
+define_machine(ws_ap3825i) {
+	.name			= "P1020 RDB",
+	.probe			= ws_ap3825i_probe,
+	.setup_arch		= ws_ap3825i_setup_arch,
+	.init_IRQ		= ws_ap3825i_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};