mpc85xx: Add Aerohive HiveAP-330 Access Point

The following adds the Aerohive HiveAP-330 Access Point to LEDE under
the mpc85xx/p1020 subtarget.

Hardware:
- SoC: Freescale P1020NSE2DFB
- NAND: Intel JS28F512M29EWH 64MB
- Memory: 2x ProMOS V59C1G01168QBJ3 128MB (Total of 256MB)
- 2.4GHz WiFi: Atheros AR9390-AL1A
- 5.0GHz WiFi: Atheros AR9390-AL1A
- Eth1: Atheros AR8035-A PoE
- Eth2: Atheros AR8035-A
- TPM: Atmel AT97SC3204
- LED Driver: TI LP5521

Flashing:
1. Hook into UART (9600 baud) and enter U-Boot. You may need to enter a
password of administrator or AhNf?d@ta06 if prompted.
2. Once in U-Boot, tftp boot the initramfs image:
    dhcp;
    tftpboot 0x1000000 192.168.1.101:lede-
mpc85xx-p1020-hiveap-330-initramfs.zImage;
    tftpboot 0x6000000 192.168.1.101:lede-mpc85xx-p1020-hiveap-330.fdt;
    bootm 0x1000000 - 0x6000000;
3. Once booted, scp over the sysupgrade file and sysupgrade the device
to flash LEDE to the NAND.
    sysupgrade /tmp/lede-mpc85xx-p1020-hiveap-330-sysupgrade.img

Signed-off-by: Chris Blake <chrisrblake93@gmail.com>

1 files changed, 89 insertions, 0 deletions

diff --git a/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c
new file mode 100644
index 0000000000..f325b32ce6
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c
@@ -0,0 +1,89 @@
+/*
+ * Aerohive HiveAP-330 Board Setup
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ *
+ * Based on:
+ *   mpc85xx_rdb.c:
+ *      MPC85xx RDB Board Setup
+ *      Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init hiveap_330_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init hiveap_330_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("hiveap_330_setup_arch()", 0);
+
+	mpc85xx_smp_init();
+
+	fsl_pci_assign_primary();
+
+	printk(KERN_INFO "HiveAP-330 board from Aerohive\n");
+}
+
+machine_arch_initcall(hiveap_330, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init hiveap_330_probe(void)
+{
+	if (of_machine_is_compatible("aerohive,hiveap-330"))
+		return 1;
+	return 0;
+}
+
+define_machine(hiveap_330) {
+	.name			= "P1020 RDB",
+	.probe			= hiveap_330_probe,
+	.setup_arch		= hiveap_330_setup_arch,
+	.init_IRQ		= hiveap_330_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};