aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/mpc83xx/patches-3.14/111-etsec27_war.patch
diff options
context:
space:
mode:
authorHauke Mehrtens <hauke@openwrt.org>2014-12-29 17:11:13 +0000
committerHauke Mehrtens <hauke@openwrt.org>2014-12-29 17:11:13 +0000
commit04a944b569277c6c675349ea9155a06eb991c47c (patch)
tree7f2fa7cd233a4b1bcee0024320929d360593c8c1 /target/linux/mpc83xx/patches-3.14/111-etsec27_war.patch
parent1bccdf44a8bc9186b6e593c98fc4fe4495ed3647 (diff)
downloadupstream-04a944b569277c6c675349ea9155a06eb991c47c.tar.gz
upstream-04a944b569277c6c675349ea9155a06eb991c47c.tar.bz2
upstream-04a944b569277c6c675349ea9155a06eb991c47c.zip
mpc83xx: add support for kernel 3.14
This is compile tested only, please run test and report back. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@43797 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/mpc83xx/patches-3.14/111-etsec27_war.patch')
-rw-r--r--target/linux/mpc83xx/patches-3.14/111-etsec27_war.patch23
1 files changed, 23 insertions, 0 deletions
diff --git a/target/linux/mpc83xx/patches-3.14/111-etsec27_war.patch b/target/linux/mpc83xx/patches-3.14/111-etsec27_war.patch
new file mode 100644
index 0000000000..0c4b3fdd77
--- /dev/null
+++ b/target/linux/mpc83xx/patches-3.14/111-etsec27_war.patch
@@ -0,0 +1,23 @@
+--- a/drivers/net/ethernet/freescale/gianfar.c
++++ b/drivers/net/ethernet/freescale/gianfar.c
+@@ -1050,10 +1050,16 @@ static int gfar_probe(struct platform_de
+ udelay(2);
+
+ tempval = 0;
+- if (!priv->pause_aneg_en && priv->tx_pause_en)
+- tempval |= MACCFG1_TX_FLOW;
+- if (!priv->pause_aneg_en && priv->rx_pause_en)
+- tempval |= MACCFG1_RX_FLOW;
++ /*
++ * Do not enable flow control on chips earlier than rev 1.1,
++ * because of the eTSEC27 erratum
++ */
++ if ((mfspr(SPRN_SVR) & 0xffff) >= 0x0011) {
++ if (!priv->pause_aneg_en && priv->tx_pause_en)
++ tempval |= MACCFG1_TX_FLOW;
++ if (!priv->pause_aneg_en && priv->rx_pause_en)
++ tempval |= MACCFG1_RX_FLOW;
++ }
+ /* the soft reset bit is not self-resetting, so we need to
+ * clear it before resuming normal operation
+ */