kernel: bump 5.15 to 5.15.75

Removed upstreamed:
   bcm27xx/patches-5.15/950-0446-drm-vc4-Fix-timings-for-VEC-modes.patch[1]

Manually rebased:
   patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
   bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch
   bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch
   bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch

All other patches automatically rebased

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.75&id=2810061452f9b748b096ad023d318690ca519aa3

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <therealgraysky@proton.me>

4 files changed, 16 insertions, 16 deletions

diff --git a/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
index 860728f02d..cfb0556d1e 100644
--- a/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
+++ b/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
@@ -47,7 +47,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
  	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  	tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
  	tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
-@@ -1436,6 +1446,16 @@ static int mtk_tphy_probe(struct platfor
+@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor
  					 &tphy->src_coef);
  	}
  
diff --git a/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch
index a5836a8268..e61b3dd94c 100644
--- a/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch
+++ b/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch
@@ -19,7 +19,7 @@
  	},
  	[PORT_NPCM] = {
  		.name		= "Nuvoton 16550",
-@@ -2745,6 +2745,11 @@ serial8250_do_set_termios(struct uart_po
+@@ -2748,6 +2748,11 @@ serial8250_do_set_termios(struct uart_po
  	unsigned long flags;
  	unsigned int baud, quot, frac = 0;
  
diff --git a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
index 4c2fd18b3b..691a7c0398 100644
--- a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
+++ b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
@@ -84,7 +84,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  static void phy_parse_property(struct mtk_tphy *tphy,
  				struct mtk_phy_instance *instance)
  {
-@@ -1143,6 +1186,40 @@ static int phy_efuse_get(struct mtk_tphy
+@@ -1144,6 +1187,40 @@ static int phy_efuse_get(struct mtk_tphy
  
  		dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
  			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
@@ -125,7 +125,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  		break;
  	default:
  		dev_err(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1174,6 +1251,31 @@ static void phy_efuse_set(struct mtk_phy
+@@ -1175,6 +1252,31 @@ static void phy_efuse_set(struct mtk_phy
  		writel(tmp, u2_banks->com + U3P_USBPHYACR1);
  		break;
  	case PHY_TYPE_USB3:
@@ -157,7 +157,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  	case PHY_TYPE_PCIE:
  		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
  		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-@@ -1195,6 +1297,34 @@ static void phy_efuse_set(struct mtk_phy
+@@ -1196,6 +1298,34 @@ static void phy_efuse_set(struct mtk_phy
  		tmp &= ~P3A_RG_IEXT_INTR;
  		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
  		writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
@@ -192,7 +192,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  		break;
  	default:
  		dev_warn(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1334,6 +1464,9 @@ static struct phy *mtk_phy_xlate(struct
+@@ -1335,6 +1465,9 @@ static struct phy *mtk_phy_xlate(struct
  	case MTK_PHY_V3:
  		phy_v2_banks_init(tphy, instance);
  		break;
@@ -202,7 +202,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  	default:
  		dev_err(dev, "phy version is not supported\n");
  		return ERR_PTR(-EINVAL);
-@@ -1374,6 +1507,12 @@ static const struct mtk_phy_pdata tphy_v
+@@ -1375,6 +1508,12 @@ static const struct mtk_phy_pdata tphy_v
  	.version = MTK_PHY_V3,
  };
  
@@ -215,7 +215,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  static const struct mtk_phy_pdata mt8173_pdata = {
  	.avoid_rx_sen_degradation = true,
  	.version = MTK_PHY_V1,
-@@ -1393,6 +1532,7 @@ static const struct of_device_id mtk_tph
+@@ -1394,6 +1533,7 @@ static const struct of_device_id mtk_tph
  	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
  	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
  	{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
diff --git a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
index 67580f1e11..3b8285bf47 100644
--- a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
+++ b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
@@ -27,7 +27,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  	u32 efuse_intr_ln1;
  	u32 efuse_tx_imp_ln1;
  	u32 efuse_rx_imp_ln1;
-@@ -1125,6 +1129,7 @@ static int phy_efuse_get(struct mtk_tphy
+@@ -1126,6 +1130,7 @@ static int phy_efuse_get(struct mtk_tphy
  {
  	struct device *dev = &instance->phy->dev;
  	int ret = 0;
@@ -35,7 +35,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  
  	/* tphy v1 doesn't support sw efuse, skip it */
  	if (!tphy->pdata->sw_efuse_supported) {
-@@ -1139,6 +1144,20 @@ static int phy_efuse_get(struct mtk_tphy
+@@ -1140,6 +1145,20 @@ static int phy_efuse_get(struct mtk_tphy
  
  	switch (instance->type) {
  	case PHY_TYPE_USB2:
@@ -56,7 +56,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
  		if (ret) {
  			dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
-@@ -1157,6 +1176,20 @@ static int phy_efuse_get(struct mtk_tphy
+@@ -1158,6 +1177,20 @@ static int phy_efuse_get(struct mtk_tphy
  
  	case PHY_TYPE_USB3:
  	case PHY_TYPE_PCIE:
@@ -77,7 +77,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
  		if (ret) {
  			dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
-@@ -1190,6 +1223,20 @@ static int phy_efuse_get(struct mtk_tphy
+@@ -1191,6 +1224,20 @@ static int phy_efuse_get(struct mtk_tphy
  		if (tphy->pdata->version != MTK_PHY_V4)
  			break;
  
@@ -98,7 +98,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  		ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
  		if (ret) {
  			dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
-@@ -1241,6 +1288,10 @@ static void phy_efuse_set(struct mtk_phy
+@@ -1242,6 +1289,10 @@ static void phy_efuse_set(struct mtk_phy
  
  	switch (instance->type) {
  	case PHY_TYPE_USB2:
@@ -109,7 +109,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  		tmp = readl(u2_banks->misc + U3P_MISC_REG1);
  		tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
  		writel(tmp, u2_banks->misc + U3P_MISC_REG1);
-@@ -1251,6 +1302,10 @@ static void phy_efuse_set(struct mtk_phy
+@@ -1252,6 +1303,10 @@ static void phy_efuse_set(struct mtk_phy
  		writel(tmp, u2_banks->com + U3P_USBPHYACR1);
  		break;
  	case PHY_TYPE_USB3:
@@ -120,7 +120,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
  		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
  		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1277,6 +1332,10 @@ static void phy_efuse_set(struct mtk_phy
+@@ -1278,6 +1333,10 @@ static void phy_efuse_set(struct mtk_phy
  
  		break;
  	case PHY_TYPE_PCIE:
@@ -131,7 +131,7 @@ Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
  		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
  		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1297,9 +1356,12 @@ static void phy_efuse_set(struct mtk_phy
+@@ -1298,9 +1357,12 @@ static void phy_efuse_set(struct mtk_phy
  		tmp &= ~P3A_RG_IEXT_INTR;
  		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
  		writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);