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| author | Thomas Reifferscheid <thomas@reifferscheid.org> | 2017-04-07 12:25:10 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2017-04-24 09:19:49 +0200 |
| commit | 8db079a9ff1756059250b801617a20baba214684 (patch) | |
| tree | 8da1d6cdf06bc845bfe9b9a4f2679cd538a9df10 /target/linux/mediatek | |
| parent | 2db05cd199999d9a3670e5287d067bdab0431f1a (diff) | |
| download | upstream-8db079a9ff1756059250b801617a20baba214684.tar.gz upstream-8db079a9ff1756059250b801617a20baba214684.tar.bz2 upstream-8db079a9ff1756059250b801617a20baba214684.zip | |
ipq8064: Fix dwc3 module unloading
The patch follows the qualcomm code comments setting
SSUSB_CTRL_TEST_POWERDOWN to 0x1 and is testing and clearing the
bit during USB superspeed PHY init. According to Andy Gross it
needs to be BIT(26).
Signed-off-by: Thomas Reifferscheid <thomas@reifferscheid.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'target/linux/mediatek')
0 files changed, 0 insertions, 0 deletions