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| author | John Crispin <john@phrozen.org> | 2020-06-04 14:20:34 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2020-06-07 17:52:21 +0200 |
| commit | 127ad76311079a842578e788a8af364f3910c676 (patch) | |
| tree | f5ffa090012853d16dcc0cf399795eb351e10d63 /target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch | |
| parent | 3559b46b626af792d8b9c41f4f2fdae5dd6c3720 (diff) | |
| download | upstream-127ad76311079a842578e788a8af364f3910c676.tar.gz upstream-127ad76311079a842578e788a8af364f3910c676.tar.bz2 upstream-127ad76311079a842578e788a8af364f3910c676.zip | |
mediatek: switch over to extended upstream eip97 driver
Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch')
| -rw-r--r-- | target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch new file mode 100644 index 0000000000..197cbf457d --- /dev/null +++ b/target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch @@ -0,0 +1,27 @@ +--- a/drivers/crypto/inside-secure/safexcel.c ++++ b/drivers/crypto/inside-secure/safexcel.c +@@ -595,6 +595,14 @@ + val |= EIP197_MST_CTRL_TX_MAX_CMD(5); + writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); + } ++ /* ++ * Set maximum number of TX commands to 2^5 = 32 for EIP97 HW2.1 ++ */ ++ else { ++ val = 0; ++ val |= EIP97_MST_CTRL_TX_MAX_CMD(5); ++ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); ++ } + + /* Configure wr/rd cache values */ + writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | +--- a/drivers/crypto/inside-secure/safexcel.h ++++ b/drivers/crypto/inside-secure/safexcel.h +@@ -306,6 +306,7 @@ + #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) + #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) + #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) ++#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) + #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) + #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) + #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) |