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| author | John Crispin <john@phrozen.org> | 2017-01-25 08:23:38 +0100 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2017-01-25 08:44:53 +0100 |
| commit | a68f6942bc539c3e27afbb40fdc726fe1affea5b (patch) | |
| tree | 966ed8ff65994ce9b46554159468363defb484b4 /target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch | |
| parent | b52932e773914ee22e848e619d11b4aaf9845feb (diff) | |
| download | upstream-a68f6942bc539c3e27afbb40fdc726fe1affea5b.tar.gz upstream-a68f6942bc539c3e27afbb40fdc726fe1affea5b.tar.bz2 upstream-a68f6942bc539c3e27afbb40fdc726fe1affea5b.zip | |
mediatek: update the ethernet compat string
mt2701 is an earlier version of the ip core, so use that compat string as
baseline.
Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch')
| -rw-r--r-- | target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch b/target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch index 7d1e7422ea..8721d770fd 100644 --- a/target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch +++ b/target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch @@ -27,7 +27,7 @@ Cc: devicetree@vger.kernel.org +* Ethernet controller node + +Required properties: -+- compatible: Should be "mediatek,mt7623-eth" ++- compatible: Should be "mediatek,mt2701-eth" +- reg: Address and length of the register set for the device +- interrupts: Should contain the frame engines interrupt +- clocks: the clock used by the core @@ -55,7 +55,7 @@ Cc: devicetree@vger.kernel.org +Example: + +eth: ethernet@1b100000 { -+ compatible = "mediatek,mt7623-eth"; ++ compatible = "mediatek,mt2701-eth"; + reg = <0 0x1b100000 0 0x20000>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <ðsys CLK_ETHSYS_ESW>, |