mediatek: bump to v4.4

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 49064

1 files changed, 1038 insertions, 0 deletions

diff --git a/target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch b/target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
new file mode 100644
index 0000000000..85ff55128f
--- /dev/null
+++ b/target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
@@ -0,0 +1,1038 @@
+From cfe366d7a20f88c7fc92faaf8b25c24e730bd40b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 5 Jan 2016 12:16:17 +0100
+Subject: [PATCH 23/53] ARM: dts: mediatek: add MT7623 basic support
+
+This adds basic chip support for Mediatek MT7623.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/arm/boot/dts/Makefile        |    1 +
+ arch/arm/boot/dts/mt7623-evb.dts  |  459 +++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623.dtsi     |  507 +++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-mediatek/Kconfig    |    4 +
+ arch/arm/mach-mediatek/mediatek.c |    1 +
+ 5 files changed, 972 insertions(+)
+ create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
+ create mode 100644 arch/arm/boot/dts/mt7623.dtsi
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 30bbc37..2bce370 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ 	mt6580-evbp1.dtb \
+ 	mt6589-aquaris5.dtb \
+ 	mt6592-evb.dtb \
++	mt7623-evb.dtb \
+ 	mt8127-moose.dtb \
+ 	mt8135-evbp1.dtb
+ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
+diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
+new file mode 100644
+index 0000000..5e9381d
+--- /dev/null
++++ b/arch/arm/boot/dts/mt7623-evb.dts
+@@ -0,0 +1,459 @@
++/*
++ * Copyright (c) 2016 MediaTek Inc.
++ * Author: John Crispin <blogic@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++/dts-v1/;
++
++#include "mt7623.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "MediaTek MT7623 evaluation board";
++	compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
++
++	chosen {
++		stdout-path = &uart2;
++	};
++
++	memory {
++		reg = <0 0x80000000 0 0x20000000>;
++	};
++
++	usb_p1_vbus: regulator@0 {
++		compatible = "regulator-fixed";
++		regulator-name = "usb_vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++	};
++};
++
++&pwrap {
++	pmic: mt6323 {
++		compatible = "mediatek,mt6323";
++		interrupt-parent = <&pio>;
++		interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-controller;
++		#interrupt-cells = <2>;
++
++		mt6323regulator: mt6323regulator{
++			compatible = "mediatek,mt6323-regulator";
++
++			mt6323_vproc_reg: buck_vproc{
++				regulator-name = "vproc";
++				regulator-min-microvolt = < 700000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <12500>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			mt6323_vsys_reg: buck_vsys{
++				regulator-name = "vsys";
++				regulator-min-microvolt = <1400000>;
++				regulator-max-microvolt = <2987500>;
++				regulator-ramp-delay = <25000>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			mt6323_vpa_reg: buck_vpa{
++				regulator-name = "vpa";
++				regulator-min-microvolt = < 500000>;
++				regulator-max-microvolt = <3650000>;
++			};
++
++			mt6323_vtcxo_reg: ldo_vtcxo{
++				regulator-name = "vtcxo";
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-enable-ramp-delay = <90>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			mt6323_vcn28_reg: ldo_vcn28{
++				regulator-name = "vcn28";
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-enable-ramp-delay = <185>;
++			};
++
++			mt6323_vcn33_bt_reg: ldo_vcn33_bt{
++				regulator-name = "vcn33_bt";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3600000>;
++				regulator-enable-ramp-delay = <185>;
++			};
++
++			mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
++				regulator-name = "vcn33_wifi";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3600000>;
++				regulator-enable-ramp-delay = <185>;
++			};
++
++			mt6323_va_reg: ldo_va{
++				regulator-name = "va";
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-enable-ramp-delay = <216>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			mt6323_vcama_reg: ldo_vcama{
++				regulator-name = "vcama";
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vio28_reg: ldo_vio28{
++				regulator-name = "vio28";
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-enable-ramp-delay = <216>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			mt6323_vusb_reg: ldo_vusb{
++				regulator-name = "vusb";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-enable-ramp-delay = <216>;
++				regulator-boot-on;
++			};
++
++			mt6323_vmc_reg: ldo_vmc{
++				regulator-name = "vmc";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-enable-ramp-delay = <36>;
++				regulator-boot-on;
++			};
++
++			mt6323_vmch_reg: ldo_vmch{
++				regulator-name = "vmch";
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-enable-ramp-delay = <36>;
++				regulator-boot-on;
++			};
++
++			mt6323_vemc3v3_reg: ldo_vemc3v3{
++				regulator-name = "vemc3v3";
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-enable-ramp-delay = <36>;
++				regulator-boot-on;
++			};
++
++			mt6323_vgp1_reg: ldo_vgp1{
++				regulator-name = "vgp1";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vgp2_reg: ldo_vgp2{
++				regulator-name = "vgp2";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vgp3_reg: ldo_vgp3{
++				regulator-name = "vgp3";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vcn18_reg: ldo_vcn18{
++				regulator-name = "vcn18";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vsim1_reg: ldo_vsim1{
++				regulator-name = "vsim1";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vsim2_reg: ldo_vsim2{
++				regulator-name = "vsim2";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vrtc_reg: ldo_vrtc{
++				regulator-name = "vrtc";
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			mt6323_vcamaf_reg: ldo_vcamaf{
++				regulator-name = "vcamaf";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vibr_reg: ldo_vibr{
++				regulator-name = "vibr";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-enable-ramp-delay = <36>;
++			};
++
++			mt6323_vrf18_reg: ldo_vrf18{
++				regulator-name = "vrf18";
++				regulator-min-microvolt = <1825000>;
++				regulator-max-microvolt = <1825000>;
++				regulator-enable-ramp-delay = <187>;
++			};
++
++			mt6323_vm_reg: ldo_vm{
++				regulator-name = "vm";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-enable-ramp-delay = <216>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			mt6323_vio18_reg: ldo_vio18{
++				regulator-name = "vio18";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-enable-ramp-delay = <216>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			mt6323_vcamd_reg: ldo_vcamd{
++				regulator-name = "vcamd";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++
++			mt6323_vcamio_reg: ldo_vcamio{
++				regulator-name = "vcamio";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-enable-ramp-delay = <216>;
++			};
++		};
++	};
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&mmc0 {
++	status = "okay";
++	pinctrl-names = "default", "state_uhs";
++	pinctrl-0 = <&mmc0_pins_default>;
++	pinctrl-1 = <&mmc0_pins_uhs>;
++	bus-width = <8>;
++	max-frequency = <50000000>;
++	cap-mmc-highspeed;
++	vmmc-supply = <&mt6323_vemc3v3_reg>;
++	vqmmc-supply = <&mt6323_vio18_reg>;
++	non-removable;
++};
++
++&mmc1 {
++	status = "okay";
++	pinctrl-names = "default", "state_uhs";
++	pinctrl-0 = <&mmc1_pins_default>;
++	pinctrl-1 = <&mmc1_pins_uhs>;
++	bus-width = <4>;
++	max-frequency = <50000000>;
++	cap-sd-highspeed;
++	sd-uhs-sdr25;
++//	cd-gpios = <&pio 132 0>;
++	vmmc-supply = <&mt6323_vmch_reg>;
++	vqmmc-supply = <&mt6323_vmc_reg>;
++};
++
++&pio {
++	mmc0_pins_default: mmc0default {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
++				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
++				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
++				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
++				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
++				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
++				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
++				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
++				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
++			input-enable;
++			bias-pull-up;
++		};
++
++		pins_clk {
++			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
++			bias-pull-down;
++		};
++
++		pins_rst {
++			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
++			bias-pull-up;
++		};
++	};
++
++	mmc0_pins_uhs: mmc0 {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
++				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
++				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
++				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
++				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
++				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
++				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
++				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
++				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
++			input-enable;
++			drive-strength = <MTK_DRIVE_2mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
++		};
++
++		pins_clk {
++			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
++			drive-strength = <MTK_DRIVE_2mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
++		};
++
++		pins_rst {
++			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
++			bias-pull-up;
++		};
++	};
++
++	mmc1_pins_default: mmc1default {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
++				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
++				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
++				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
++				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
++			input-enable;
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
++		};
++
++		pins_clk {
++			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
++			bias-pull-down;
++			drive-strength = <MTK_DRIVE_4mA>;
++		};
++
++//		pins_insert {
++//			pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
++//			bias-pull-up;
++//		};
++	};
++
++	mmc1_pins_uhs: mmc1 {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
++				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
++				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
++				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
++				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
++			input-enable;
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
++		};
++
++		pins_clk {
++			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
++		};
++	};
++
++	eth_default: eth {
++		pins_eth {
++			pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
++				 <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
++				 <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
++				 <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
++				 <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
++				 <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
++				 <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
++				 <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
++				 <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
++				 <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
++				 <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
++				 <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
++				 <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
++				 <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
++				 <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
++		};
++		
++		pins_eth_rst {
++			pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
++			output-low;
++		};
++	};
++};
++
++&usb1 {
++	vusb33-supply = <&mt6323_vusb_reg>;
++	vbus-supply = <&usb_p1_vbus>;
++//	mediatek,wakeup-src = <1>;
++	status = "okay";
++};
++
++&u3phy1 {
++	status = "okay";
++};
++
++&pcie {
++	status = "okay";
++};
++
++&eth {
++	status = "okay";
++};
++
++&gmac1 {
++	mac-address = [00 11 22 33 44 56];
++	status = "okay";
++};
++
++&gmac2 {
++	mac-address = [00 11 22 33 44 55];
++	status = "okay";
++};
++
++&gsw {
++	pinctrl-names = "default";
++	pinctrl-0 = <&eth_default>;
++	mediatek,reset-pin = <&pio 15 0>;
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
+new file mode 100644
+index 0000000..1ba7790
+--- /dev/null
++++ b/arch/arm/boot/dts/mt7623.dtsi
+@@ -0,0 +1,507 @@
++/*
++ * Copyright (c) 2016 MediaTek Inc.
++ * Author: John Crispin <blogic@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/clock/mt2701-clk.h>
++#include <dt-bindings/power/mt2701-power.h>
++#include <dt-bindings/phy/phy.h>
++#include <dt-bindings/reset-controller/mt2701-resets.h>
++#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
++#include "skeleton64.dtsi"
++
++
++/ {
++	compatible = "mediatek,mt7623";
++	interrupt-parent = <&sysirq>;
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a7";
++			reg = <0x0>;
++		};
++		cpu@1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a7";
++			reg = <0x1>;
++		};
++		cpu@2 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a7";
++			reg = <0x2>;
++		};
++		cpu@3 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a7";
++			reg = <0x3>;
++		};
++	};
++
++	system_clk: dummy13m {
++		compatible = "fixed-clock";
++		clock-frequency = <13000000>;
++		#clock-cells = <0>;
++	};
++
++	rtc_clk: dummy32k {
++		compatible = "fixed-clock";
++		clock-frequency = <32000>;
++		#clock-cells = <0>;
++		clock-output-names = "clk32k";
++	};
++
++	clk26m: dummy26m {
++		compatible = "fixed-clock";
++		clock-frequency = <26000000>;
++		#clock-cells = <0>;
++		clock-output-names = "clk26m";
++	};
++
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupt-parent = <&gic>;
++		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
++			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
++			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
++			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++	};
++
++	topckgen: power-controller@10000000 {
++		compatible = "mediatek,mt7623-topckgen",
++			     "mediatek,mt2701-topckgen",
++			     "syscon";
++		reg = <0 0x10000000 0 0x1000>;
++		#clock-cells = <1>;
++	};
++
++	infracfg: power-controller@10001000 {
++		compatible = "mediatek,mt7623-infracfg",
++			     "mediatek,mt2701-infracfg",
++			     "syscon";
++		reg = <0 0x10001000 0 0x1000>;
++		#clock-cells = <1>;
++		#reset-cells = <1>;
++	};
++
++	pericfg: pericfg@10003000 {
++		compatible = "mediatek,mt7623-pericfg",
++			     "mediatek,mt2701-pericfg",
++			     "syscon";
++		reg = <0 0x10003000 0 0x1000>;
++		#clock-cells = <1>;
++		#reset-cells = <1>;
++	};
++
++	pio: pinctrl@10005000 {
++		compatible = "mediatek,mt7623-pinctrl";
++		reg = <0 0x1000b000 0 0x1000>;
++		mediatek,pctl-regmap = <&syscfg_pctl_a>;
++		pins-are-numbered;
++		gpio-controller;
++		#gpio-cells = <2>;
++		interrupt-controller;
++		interrupt-parent = <&gic>;
++		#interrupt-cells = <2>;
++		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	syscfg_pctl_a: syscfg@10005000 {
++		compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
++		reg = <0 0x10005000 0 0x1000>;
++	};
++
++	scpsys: scpsys@10006000 {
++		#power-domain-cells = <1>;
++		compatible = "mediatek,mt7623-scpsys",
++			     "mediatek,mt2701-scpsys";
++		reg = <0 0x10006000 0 0x1000>;
++		infracfg = <&infracfg>;
++		clocks = <&clk26m>,
++			 <&topckgen CLK_TOP_MM_SEL>;
++		clock-names = "mfg", "mm";
++	};
++
++	watchdog: watchdog@10007000 {
++		compatible = "mediatek,mt7623-wdt",
++			     "mediatek,mt6589-wdt";
++		reg = <0 0x10007000 0 0x100>;
++	};
++
++	timer: timer@10008000 {
++		compatible = "mediatek,mt7623-timer",
++			     "mediatek,mt6577-timer";
++		reg = <0 0x10008000 0 0x80>;
++		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&system_clk>, <&rtc_clk>;
++		clock-names = "system-clk", "rtc-clk";
++	};
++
++	pwrap: pwrap@1000d000 {
++		compatible = "mediatek,mt7623-pwrap",
++			     "mediatek,mt2701-pwrap";
++		reg = <0 0x1000d000 0 0x1000>;
++		reg-names = "pwrap";
++		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
++		resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
++		reset-names = "pwrap";
++		clocks = <&infracfg CLK_INFRA_PMICSPI>,
++			 <&infracfg CLK_INFRA_PMICWRAP>;
++		clock-names = "spi", "wrap";
++	};
++
++	sysirq: interrupt-controller@10200100 {
++		compatible = "mediatek,mt7623-sysirq",
++			     "mediatek,mt6577-sysirq";
++		interrupt-controller;
++		#interrupt-cells = <3>;
++		interrupt-parent = <&gic>;
++		reg = <0 0x10200100 0 0x1c>;
++	};
++
++	apmixedsys: apmixedsys@10209000 {
++		compatible = "mediatek,mt7623-apmixedsys",
++			     "mediatek,mt2701-apmixedsys";
++		reg = <0 0x10209000 0 0x1000>;
++		#clock-cells = <1>;
++	};
++
++	gic: interrupt-controller@10211000 {
++		compatible = "arm,cortex-a7-gic";
++		interrupt-controller;
++		#interrupt-cells = <3>;
++		interrupt-parent = <&gic>;
++		reg = <0 0x10211000 0 0x1000>,
++		      <0 0x10212000 0 0x1000>,
++		      <0 0x10214000 0 0x2000>,
++		      <0 0x10216000 0 0x2000>;
++	};
++
++	i2c0: i2c@11007000 {
++		compatible = "mediatek,mt7623-i2c",
++			     "mediatek,mt6577-i2c";
++		reg = <0 0x11007000 0 0x70>,
++		      <0 0x11000200 0 0x80>;
++		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
++		clock-div = <16>;
++		clocks = <&pericfg CLK_PERI_I2C0>,
++			 <&pericfg CLK_PERI_AP_DMA>;
++		clock-names = "main", "dma";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	i2c1: i2c@11008000 {
++		compatible = "mediatek,mt7623-i2c",
++			     "mediatek,mt6577-i2c";
++		reg = <0 0x11008000 0 0x70>,
++		      <0 0x11000280 0 0x80>;
++		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
++		clock-div = <16>;
++		clocks = <&pericfg CLK_PERI_I2C1>,
++			 <&pericfg CLK_PERI_AP_DMA>;
++		clock-names = "main", "dma";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	i2c2: i2c@11009000 {
++		compatible = "mediatek,mt7623-i2c",
++			     "mediatek,mt6577-i2c";
++		reg = <0 0x11009000 0 0x70>,
++		      <0 0x11000300 0 0x80>;
++		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
++		clock-div = <16>;
++		clocks = <&pericfg CLK_PERI_I2C2>,
++			 <&pericfg CLK_PERI_AP_DMA>;
++		clock-names = "main", "dma";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	uart0: serial@11002000 {
++		compatible = "mediatek,mt7623-uart",
++			     "mediatek,mt6577-uart";
++		reg = <0 0x11002000 0 0x400>;
++		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_UART0_SEL>,
++			 <&pericfg CLK_PERI_UART0>;
++		clock-names = "baud", "bus";
++		status = "disabled";
++	};
++
++	uart1: serial@11003000 {
++		compatible = "mediatek,mt7623-uart",
++			     "mediatek,mt6577-uart";
++		reg = <0 0x11003000 0 0x400>;
++		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_UART1_SEL>,
++			 <&pericfg CLK_PERI_UART1>;
++		clock-names = "baud", "bus";
++		status = "disabled";
++	};
++
++	uart2: serial@11004000 {
++		compatible = "mediatek,mt7623-uart",
++			     "mediatek,mt6577-uart";
++		reg = <0 0x11004000 0 0x400>;
++		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_UART2_SEL>,
++			 <&pericfg CLK_PERI_UART2>;
++		clock-names = "baud", "bus";
++		status = "disabled";
++	};
++
++	uart3: serial@11005000 {
++		compatible = "mediatek,mt7623-uart",
++			     "mediatek,mt6577-uart";
++		reg = <0 0x11005000 0 0x400>;
++		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_UART3_SEL>,
++			 <&pericfg CLK_PERI_UART3>;
++		clock-names = "baud", "bus";
++		status = "disabled";
++	};
++
++	spi: spi@1100a000 {
++		compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
++		reg = <0 0x1100a000 0 0x1000>;
++		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_SPI0>;
++		clock-names = "main";
++
++		status = "disabled";
++	};
++
++	mmc0: mmc@11230000 {
++		compatible = "mediatek,mt7623-mmc",
++			     "mediatek,mt8135-mmc";
++		reg = <0 0x11230000 0 0x1000>;
++		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_MSDC30_0>,
++			 <&topckgen CLK_TOP_MSDC30_0_SEL>;
++		clock-names = "source", "hclk";
++		status = "disabled";
++	};
++
++	mmc1: mmc@11240000 {
++		compatible = "mediatek,mt7623-mmc",
++			     "mediatek,mt8135-mmc";
++		reg = <0 0x11240000 0 0x1000>;
++		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_MSDC30_1>,
++			 <&topckgen CLK_TOP_MSDC30_1_SEL>;
++		clock-names = "source", "hclk";
++		status = "disabled";
++	};
++
++	usb1: usb@1a1c0000 {
++		compatible = "mediatek,mt2701-xhci",
++			     "mediatek,mt8173-xhci";
++		reg = <0 0x1a1c0000 0 0x1000>,
++		      <0 0x1a1c4700 0 0x0100>;
++		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
++			 <&topckgen CLK_TOP_ETHIF_SEL>;
++		clock-names = "sys_ck", "ethif";
++		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
++		phys = <&phy_port0 PHY_TYPE_USB3>;
++		status = "disabled";
++	};
++
++	u3phy1: usb-phy@1a1c4000 {
++		compatible = "mediatek,mt2701-u3phy",
++			     "mediatek,mt8173-u3phy";
++		reg = <0 0x1a1c4000 0 0x0700>;
++		clocks = <&clk26m>;
++		clock-names = "u3phya_ref";
++		#phy-cells = <1>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		status = "disabled";
++
++		phy_port0: phy_port0: port@1a1c4800 {
++			reg = <0 0x1a1c4800 0 0x800>;
++			#phy-cells = <1>;
++			status = "okay";
++		};
++	};
++
++	usb2: usb@1a240000 {
++		compatible = "mediatek,mt2701-xhci",
++			     "mediatek,mt8173-xhci";
++		reg = <0 0x1a240000 0 0x1000>,
++		      <0 0x1a244700 0 0x0100>;
++		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
++			 <&topckgen CLK_TOP_ETHIF_SEL>;
++		clock-names = "sys_ck", "ethif";
++		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
++		phys = <&u3phy2 0>;
++		status = "disabled";
++	};
++
++	u3phy2: usb-phy@1a244000 {
++		compatible = "mediatek,mt2701-u3phy",
++			     "mediatek,mt8173-u3phy";
++		reg = <0 0x1a244000 0 0x0700>,
++		      <0 0x1a244800 0 0x0800>;
++		clocks = <&clk26m>;
++		clock-names = "u3phya_ref";
++		#phy-cells = <1>;
++		status = "disabled";
++	};
++
++	hifsys: clock-controller@1a000000 {
++		compatible = "mediatek,mt7623-hifsys",
++			     "mediatek,mt2701-hifsys",
++			     "syscon";
++		reg = <0 0x1a000000 0 0x1000>;
++		#clock-cells = <1>;
++		#reset-cells = <1>;
++	};
++
++	pcie: pcie@1a140000 {
++		compatible = "mediatek,mt7623-pcie";
++		device_type = "pci";
++		reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
++		      <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
++		      <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
++		      <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
++		reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
++		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
++			     <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
++			     <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-names = "pcie0", "pcie1", "pcie2";
++		clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
++		clock-names = "pcie";
++		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
++		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
++			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
++			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
++		reset-names = "pcie0", "pcie1", "pcie2";
++
++		mediatek,hifsys = <&hifsys>;
++
++		bus-range = <0x00 0xff>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
++			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
++
++		status = "disabled";
++
++		pcie@1,0 {
++			device_type = "pci";
++			reg = <0x0800 0 0 0 0>;
++
++			#address-cells = <3>;
++			#size-cells = <2>;
++			ranges;
++		};
++
++		pcie@2,0{
++			device_type = "pci";
++			reg = <0x1000 0 0 0 0>;
++
++			#address-cells = <3>;
++			#size-cells = <2>;
++			ranges;
++		};
++
++		pcie@3,0{
++			device_type = "pci";
++			reg = <0x1800 0 0 0 0>;
++
++			#address-cells = <3>;
++			#size-cells = <2>;
++			ranges;
++		};
++	};
++
++	ethsys: syscon@1b000000 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "mediatek,mt2701-ethsys", "syscon";
++		reg = <0 0x1b000000 0 0x1000>;
++		#clock-cells = <1>;
++	};
++
++	eth: ethernet@1b100000 {
++		compatible = "mediatek,mt7623-eth";
++		reg = <0 0x1b100000 0 0x10000>;
++	
++		clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
++		clock-names = "ethif";
++		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
++		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
++
++		mediatek,ethsys = <&ethsys>;
++		mediatek,switch = <&gsw>;
++
++		#address-cells = <1>;
++		#size-cells = <0>;
++	
++		status = "disabled";
++
++		gmac1: mac@0 {
++			compatible = "mediatek,eth-mac";
++			reg = <0>;
++
++			status = "disabled";
++		};
++
++		gmac2: mac@1 {
++			compatible = "mediatek,eth-mac";
++			reg = <1>;
++
++			status = "disabled";
++		};
++	
++		mdio-bus {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			phy1f: ethernet-phy@1f {
++				reg = <0x1f>;
++				phy-mode = "rgmii";
++			};
++		};
++	};
++
++	gsw: switch@1b100000 {
++		compatible = "mediatek,mt7623-gsw";
++		reg = <0 0x1b110000 0 0x300000>;
++		interrupt-parent = <&pio>;
++		interrupts = <168 IRQ_TYPE_EDGE_RISING>;
++		clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
++			 <&ethsys CLK_ETHSYS_ESW>,
++			 <&ethsys CLK_ETHSYS_GP2>,
++			 <&ethsys CLK_ETHSYS_GP1>;
++		clock-names = "trgpll", "esw", "gp2", "gp1";
++		mt7530-supply = <&mt6323_vpa_reg>;
++		mediatek,pctl-regmap = <&syscfg_pctl_a>;
++		mediatek,ethsys = <&ethsys>;
++		status = "disabled";
++	};
++};
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index 37dd438..7fb605e 100644
+--- a/arch/arm/mach-mediatek/Kconfig
++++ b/arch/arm/mach-mediatek/Kconfig
+@@ -21,6 +21,10 @@ config MACH_MT6592
+ 	bool "MediaTek MT6592 SoCs support"
+ 	default ARCH_MEDIATEK
+ 
++config MACH_MT7623
++	bool "MediaTek MT7623 SoCs support"
++	default ARCH_MEDIATEK
++
+ config MACH_MT8127
+ 	bool "MediaTek MT8127 SoCs support"
+ 	default ARCH_MEDIATEK
+diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
+index d019a08..bcfca37 100644
+--- a/arch/arm/mach-mediatek/mediatek.c
++++ b/arch/arm/mach-mediatek/mediatek.c
+@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
+ static const char * const mediatek_board_dt_compat[] = {
+ 	"mediatek,mt6589",
+ 	"mediatek,mt6592",
++	"mediatek,mt7623",
+ 	"mediatek,mt8127",
+ 	"mediatek,mt8135",
+ 	NULL,
+-- 
+1.7.10.4
+