aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
diff options
context:
space:
mode:
authorJohn Crispin <john@openwrt.org>2016-04-26 11:43:38 +0000
committerJohn Crispin <john@openwrt.org>2016-04-26 11:43:38 +0000
commit301d48b8f03c7460efac50007154ab2426db188a (patch)
tree3b0e00138bd3020f682470e90bcf357cd2529a2f /target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
parent0a4f2b5920a8c4fa5afc021bc95a6aa781984013 (diff)
downloadupstream-301d48b8f03c7460efac50007154ab2426db188a.tar.gz
upstream-301d48b8f03c7460efac50007154ab2426db188a.tar.bz2
upstream-301d48b8f03c7460efac50007154ab2426db188a.zip
mediatek: update patches
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 49243
Diffstat (limited to 'target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch')
-rw-r--r--target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch151
1 files changed, 127 insertions, 24 deletions
diff --git a/target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch b/target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
index 2432c21490..41aad5c741 100644
--- a/target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
+++ b/target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
@@ -1,21 +1,23 @@
-From a4df3e7e4e906a4e9dac1f8c43f6192f22ef6242 Mon Sep 17 00:00:00 2001
+From 5536a546755527a862cb2494814c5244d3d8e30a Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 5 Jan 2016 12:16:17 +0100
-Subject: [PATCH 23/81] ARM: dts: mediatek: add MT7623 basic support
+Subject: [PATCH 23/91] ARM: dts: mediatek: add MT7623 basic support
This adds basic chip support for Mediatek MT7623.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/mt7623-evb.dts | 459 +++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623.dtsi | 510 +++++++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623-evb.dts | 474 ++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623.dtsi | 583 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 4 +
arch/arm/mach-mediatek/mediatek.c | 1 +
- 5 files changed, 975 insertions(+)
+ 5 files changed, 1063 insertions(+)
create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
create mode 100644 arch/arm/boot/dts/mt7623.dtsi
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 30bbc37..2bce370 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -26,9 +28,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
+diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
+new file mode 100644
+index 0000000..70b92a4
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623-evb.dts
-@@ -0,0 +1,459 @@
+@@ -0,0 +1,474 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic@openwrt.org>
@@ -70,6 +75,22 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ };
+};
+
++&cpu0 {
++ proc-supply = <&mt6323_vproc_reg>;
++};
++
++&cpu1 {
++ proc-supply = <&mt6323_vproc_reg>;
++};
++
++&cpu2 {
++ proc-supply = <&mt6323_vproc_reg>;
++};
++
++&cpu3 {
++ proc-supply = <&mt6323_vproc_reg>;
++};
++
+&pwrap {
+ pmic: mt6323 {
+ compatible = "mediatek,mt6323";
@@ -456,7 +477,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+&usb1 {
+ vusb33-supply = <&mt6323_vusb_reg>;
+ vbus-supply = <&usb_p1_vbus>;
-+// mediatek,wakeup-src = <1>;
+ status = "okay";
+};
+
@@ -488,9 +508,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ mediatek,reset-pin = <&pio 15 0>;
+ status = "okay";
+};
+diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
+new file mode 100644
+index 0000000..0536b2c
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -0,0 +1,510 @@
+@@ -0,0 +1,583 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic@openwrt.org>
@@ -524,25 +547,65 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
-+ cpu@0 {
++ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
++ clocks = <&infracfg CLK_INFRA_CPUSEL>,
++ <&apmixedsys CLK_APMIXED_MAINPLL>;
++ clock-names = "cpu", "intermediate";
++ operating-points = <
++ 598000 1150000
++ 747500 1150000
++ 1040000 1150000
++ 1196000 1200000
++ 1300000 1300000
++ >;
+ };
-+ cpu@1 {
++ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
++ clocks = <&infracfg CLK_INFRA_CPUSEL>,
++ <&apmixedsys CLK_APMIXED_MAINPLL>;
++ clock-names = "cpu", "intermediate";
++ operating-points = <
++ 598000 1150000
++ 747500 1150000
++ 1040000 1150000
++ 1196000 1200000
++ 1300000 1300000
++ >;
+ };
-+ cpu@2 {
++ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
++ clocks = <&infracfg CLK_INFRA_CPUSEL>,
++ <&apmixedsys CLK_APMIXED_MAINPLL>;
++ clock-names = "cpu", "intermediate";
++ operating-points = <
++ 598000 1150000
++ 747500 1150000
++ 1040000 1150000
++ 1196000 1200000
++ 1300000 1300000
++ >;
+ };
-+ cpu@3 {
++ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
++ clocks = <&infracfg CLK_INFRA_CPUSEL>,
++ <&apmixedsys CLK_APMIXED_MAINPLL>;
++ clock-names = "cpu", "intermediate";
++ operating-points = <
++ 598000 1150000
++ 747500 1150000
++ 1040000 1150000
++ 1196000 1200000
++ 1300000 1300000
++ >;
+ };
+ };
+
@@ -573,6 +636,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++ clock-frequency = <13000000>;
++ arm,cpu-registers-not-fw-configured;
+ };
+
+ topckgen: power-controller@10000000 {
@@ -785,6 +850,18 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ status = "disabled";
+ };
+
++ nand: nfi@1100d000 {
++ compatible = "mediatek,mt2701-nfc";
++ reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
++ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
++ <&pericfg CLK_PERI_NFI_PAD>;
++ clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
++ // nand-on-flash-bbt;
++ status = "disabled";
++ };
++
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7623-mmc",
+ "mediatek,mt8135-mmc";
@@ -934,25 +1011,32 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ };
+
+ ethsys: syscon@1b000000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
+ compatible = "mediatek,mt2701-ethsys", "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
++ #reset-cells = <1>;
+ #clock-cells = <1>;
+ };
+
+ eth: ethernet@1b100000 {
+ compatible = "mediatek,mt7623-eth";
-+ reg = <0 0x1b100000 0 0x10000>;
++ reg = <0 0x1b100000 0 0x20000>;
+
-+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
-+ clock-names = "ethif";
++ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
++ <&ethsys CLK_ETHSYS_ESW>,
++ <&ethsys CLK_ETHSYS_GP2>,
++ <&ethsys CLK_ETHSYS_GP1>;
++ clock-names = "ethif", "esw", "gp2", "gp1";
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
+ GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
+ GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+
++ resets = <&ethsys 6>;
++ reset-names = "eth";
++
+ mediatek,ethsys = <&ethsys>;
++ mediatek,pctl = <&syscfg_pctl_a>;
++
+ mediatek,switch = <&gsw>;
+
+ #address-cells = <1>;
@@ -965,12 +1049,21 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ reg = <0>;
+
+ status = "disabled";
++
++ phy-mode = "rgmii";
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ pause;
++ };
+ };
+
+ gmac2: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+
++ phy-handle = <&phy5>;
+ status = "disabled";
+ };
+
@@ -978,6 +1071,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ #address-cells = <1>;
+ #size-cells = <0>;
+
++ phy5: ethernet-phy@5 {
++ reg = <5>;
++ phy-mode = "rgmii-rxid";
++ };
++
+ phy1f: ethernet-phy@1f {
+ reg = <0x1f>;
+ phy-mode = "rgmii";
@@ -987,20 +1085,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+ gsw: switch@1b100000 {
+ compatible = "mediatek,mt7623-gsw";
-+ reg = <0 0x1b110000 0 0x300000>;
+ interrupt-parent = <&pio>;
+ interrupts = <168 IRQ_TYPE_EDGE_RISING>;
-+ clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
-+ <&ethsys CLK_ETHSYS_ESW>,
-+ <&ethsys CLK_ETHSYS_GP2>,
-+ <&ethsys CLK_ETHSYS_GP1>;
-+ clock-names = "trgpll", "esw", "gp2", "gp1";
++ resets = <&ethsys 2>;
++ reset-names = "eth";
++ clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
++ clock-names = "trgpll";
+ mt7530-supply = <&mt6323_vpa_reg>;
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
+ mediatek,ethsys = <&ethsys>;
+ status = "disabled";
+ };
+};
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index 37dd438..7fb605e 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -21,6 +21,10 @@ config MACH_MT6592
@@ -1014,9 +1112,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
config MACH_MT8127
bool "MediaTek MT8127 SoCs support"
default ARCH_MEDIATEK
+diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
+index d019a08..bcfca37 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
-@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
+@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
static const char * const mediatek_board_dt_compat[] = {
"mediatek,mt6589",
"mediatek,mt6592",
@@ -1024,3 +1124,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
"mediatek,mt8127",
"mediatek,mt8135",
NULL,
+--
+1.7.10.4
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 06:57:48 +0000