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authorJohn Crispin <john@openwrt.org>2016-03-21 20:42:51 +0000
committerJohn Crispin <john@openwrt.org>2016-03-21 20:42:51 +0000
commit5d2f529c9b83d5f769258928b5ddd82f4dc9979e (patch)
tree65ecb999d7bfda861006ffba75f375c1d7c8260d /target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch
parentc8a6c583fc5f5c0834f993b591d6bb52d958c99a (diff)
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mediatek: bump to v4.4
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 49064
Diffstat (limited to 'target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch')
-rw-r--r--target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch99
1 files changed, 99 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch b/target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch
new file mode 100644
index 0000000000..c78d7f8aad
--- /dev/null
+++ b/target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch
@@ -0,0 +1,99 @@
+From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
+From: Shunli Wang <shunli.wang@mediatek.com>
+Date: Tue, 5 Jan 2016 14:30:21 +0800
+Subject: [PATCH 10/53] reset: mediatek: mt2701 reset controller dt-binding
+ file
+
+Dt-binding file about reset controller is used to provide
+kinds of definition, which is referenced by dts file and
+IC-specified reset controller driver code.
+
+Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
+---
+ .../dt-bindings/reset-controller/mt2701-resets.h | 74 ++++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+ create mode 100644 include/dt-bindings/reset-controller/mt2701-resets.h
+
+diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
+new file mode 100644
+index 0000000..00efeb0
+--- /dev/null
++++ b/include/dt-bindings/reset-controller/mt2701-resets.h
+@@ -0,0 +1,74 @@
++/*
++ * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
++#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
++
++/* INFRACFG resets */
++#define MT2701_INFRA_EMI_REG_RST 0
++#define MT2701_INFRA_DRAMC0_A0_RST 1
++#define MT2701_INFRA_FHCTL_RST 2
++#define MT2701_INFRA_APCIRQ_EINT_RST 3
++#define MT2701_INFRA_APXGPT_RST 4
++#define MT2701_INFRA_SCPSYS_RST 5
++#define MT2701_INFRA_KP_RST 6
++#define MT2701_INFRA_PMIC_WRAP_RST 7
++#define MT2701_INFRA_MIPI_RST 8
++#define MT2701_INFRA_IRRX_RST 9
++#define MT2701_INFRA_CEC_RST 10
++#define MT2701_INFRA_EMI_RST 32
++#define MT2701_INFRA_DRAMC0_RST 34
++#define MT2701_INFRA_TRNG_RST 37
++#define MT2701_INFRA_SYSIRQ_RST 38
++
++/* PERICFG resets */
++#define MT2701_PERI_UART0_SW_RST 0
++#define MT2701_PERI_UART1_SW_RST 1
++#define MT2701_PERI_UART2_SW_RST 2
++#define MT2701_PERI_UART3_SW_RST 3
++#define MT2701_PERI_GCPU_SW_RST 5
++#define MT2701_PERI_BTIF_SW_RST 6
++#define MT2701_PERI_PWM_SW_RST 8
++#define MT2701_PERI_AUXADC_SW_RST 10
++#define MT2701_PERI_DMA_SW_RST 11
++#define MT2701_PERI_NFI_SW_RST 14
++#define MT2701_PERI_NLI_SW_RST 15
++#define MT2701_PERI_THERM_SW_RST 16
++#define MT2701_PERI_MSDC2_SW_RST 17
++#define MT2701_PERI_MSDC0_SW_RST 19
++#define MT2701_PERI_MSDC1_SW_RST 20
++#define MT2701_PERI_I2C0_SW_RST 22
++#define MT2701_PERI_I2C1_SW_RST 23
++#define MT2701_PERI_I2C2_SW_RST 24
++#define MT2701_PERI_I2C3_SW_RST 25
++#define MT2701_PERI_USB_SW_RST 28
++#define MT2701_PERI_ETH_SW_RST 29
++#define MT2701_PERI_SPI0_SW_RST 33
++
++/* TOPRGU resets */
++#define MT2701_TOPRGU_INFRA_RST 0
++#define MT2701_TOPRGU_MM_RST 1
++#define MT2701_TOPRGU_MFG_RST 2
++#define MT2701_TOPRGU_ETHDMA_RST 3
++#define MT2701_TOPRGU_VDEC_RST 4
++#define MT2701_TOPRGU_VENC_IMG_RST 5
++#define MT2701_TOPRGU_DDRPHY_RST 6
++#define MT2701_TOPRGU_MD_RST 7
++#define MT2701_TOPRGU_INFRA_AO_RST 8
++#define MT2701_TOPRGU_CONN_RST 9
++#define MT2701_TOPRGU_APMIXED_RST 10
++#define MT2701_TOPRGU_HIFSYS_RST 11
++#define MT2701_TOPRGU_CONN_MCU_RST 12
++#define MT2701_TOPRGU_BDP_DISP_RST 13
++
++#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
+--
+1.7.10.4
+