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authorJohn Crispin <john@phrozen.org>2018-05-07 12:07:32 +0200
committerJohn Crispin <john@phrozen.org>2018-05-24 22:11:55 +0200
commit050da2107a7eb2a571a8a3d0cee21cc6a44b72b8 (patch)
tree147c3b85ccae12e4b1659acd86ac93b13ecfa15d /target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch
parent4f67c1522d92bc4512c3ecf58c38ff9886530b48 (diff)
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mediatek: backport upstream mediatek patches
Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch')
-rw-r--r--target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch91
1 files changed, 91 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch b/target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch
new file mode 100644
index 0000000000..82b523c9d1
--- /dev/null
+++ b/target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch
@@ -0,0 +1,91 @@
+From 4fbacf244953285ac58cb833060076fafd990588 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Fri, 29 Dec 2017 10:45:07 +0800
+Subject: [PATCH 218/224] arm64: dts: mt7622: add ethernet device nodes
+
+add ethernet device nodes which enable GMAC1 with SGMII interface
+
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 22 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 31 ++++++++++++++++++++++++++++
+ 2 files changed, 53 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+index 48c5ba472721..e2bd93e1b49b 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -249,6 +249,28 @@
+ status = "okay";
+ };
+
++&eth {
++ pinctrl-names = "default";
++ pinctrl-0 = <&eth_pins>;
++ status = "okay";
++
++ gmac1: mac@1 {
++ compatible = "mediatek,eth-mac";
++ reg = <1>;
++ phy-handle = <&phy5>;
++ };
++
++ mdio-bus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy5: ethernet-phy@5 {
++ reg = <5>;
++ phy-mode = "sgmii";
++ };
++ };
++};
++
+ &i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+index d287d75e1a54..95f947eb824c 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -550,6 +550,37 @@
+ #reset-cells = <1>;
+ };
+
++ eth: ethernet@1b100000 {
++ compatible = "mediatek,mt7622-eth",
++ "mediatek,mt2701-eth",
++ "syscon";
++ reg = <0 0x1b100000 0 0x20000>;
++ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&topckgen CLK_TOP_ETH_SEL>,
++ <&ethsys CLK_ETH_ESW_EN>,
++ <&ethsys CLK_ETH_GP0_EN>,
++ <&ethsys CLK_ETH_GP1_EN>,
++ <&ethsys CLK_ETH_GP2_EN>,
++ <&sgmiisys CLK_SGMII_TX250M_EN>,
++ <&sgmiisys CLK_SGMII_RX250M_EN>,
++ <&sgmiisys CLK_SGMII_CDR_REF>,
++ <&sgmiisys CLK_SGMII_CDR_FB>,
++ <&topckgen CLK_TOP_SGMIIPLL>,
++ <&apmixedsys CLK_APMIXED_ETH2PLL>;
++ clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
++ "sgmii_tx250m", "sgmii_rx250m",
++ "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
++ "eth2pll";
++ power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
++ mediatek,ethsys = <&ethsys>;
++ mediatek,sgmiisys = <&sgmiisys>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ sgmiisys: sgmiisys@1b128000 {
+ compatible = "mediatek,mt7622-sgmiisys",
+ "syscon";
+--
+2.11.0
+