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authorJohn Crispin <john@phrozen.org>2018-05-07 12:07:32 +0200
committerJohn Crispin <john@phrozen.org>2018-05-24 22:11:55 +0200
commit050da2107a7eb2a571a8a3d0cee21cc6a44b72b8 (patch)
tree147c3b85ccae12e4b1659acd86ac93b13ecfa15d /target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch
parent4f67c1522d92bc4512c3ecf58c38ff9886530b48 (diff)
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mediatek: backport upstream mediatek patches
Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch')
-rw-r--r--target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch50
1 files changed, 50 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch b/target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch
new file mode 100644
index 0000000000..362d40db15
--- /dev/null
+++ b/target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch
@@ -0,0 +1,50 @@
+From 79d0293e8f35e87b1f068fc0b7963a86ba56800e Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Thu, 28 Dec 2017 15:46:42 +0800
+Subject: [PATCH 211/224] arm64: dts: mt7622: add power domain controller
+ device nodes
+
+add power domain controller nodes
+
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Cc: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+index 73e5d628a8c8..81207e652d59 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt7622-clk.h>
++#include <dt-bindings/power/mt7622-power.h>
+ #include <dt-bindings/reset/mt7622-reset.h>
+
+ / {
+@@ -109,6 +110,20 @@
+ #reset-cells = <1>;
+ };
+
++ scpsys: scpsys@10006000 {
++ compatible = "mediatek,mt7622-scpsys",
++ "syscon";
++ #power-domain-cells = <1>;
++ reg = <0 0x10006000 0 0x1000>;
++ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
++ infracfg = <&infracfg>;
++ clocks = <&topckgen CLK_TOP_HIF_SEL>;
++ clock-names = "hif_sel";
++ };
++
+ sysirq: interrupt-controller@10200620 {
+ compatible = "mediatek,mt7622-sysirq",
+ "mediatek,mt6577-sysirq";
+--
+2.11.0
+