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authorHauke Mehrtens <hauke@hauke-m.de>2020-01-04 00:36:43 +0100
committerHauke Mehrtens <hauke@hauke-m.de>2020-01-04 23:04:24 +0100
commit084dfb8ebdb8fe124189cf498aea3f0269daee16 (patch)
tree155b0821212d0fdeb8dbbf33e37252fe1a7df0e0 /target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch
parentf8543adb149830a4549cf8691a02167e5d7cec95 (diff)
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kernel: bump 4.14 to 4.14.161
Refreshed all patches. Compile-tested on: ipq40xx, ramips Runtime-tested on: ipq40xx Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch')
-rw-r--r--target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch10
1 files changed, 5 insertions, 5 deletions
diff --git a/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch b/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch
index 63aef198c2..21a0c90486 100644
--- a/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch
+++ b/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch
@@ -23,7 +23,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
#define SDC_FIFO_CFG 0x228
/*--------------------------------------------------------------------------*/
-@@ -249,6 +250,8 @@
+@@ -251,6 +252,8 @@
#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
@@ -32,7 +32,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
-@@ -318,6 +321,7 @@ struct msdc_save_para {
+@@ -320,6 +323,7 @@ struct msdc_save_para {
u32 pad_ds_tune;
u32 pad_cmd_tune;
u32 emmc50_cfg0;
@@ -40,7 +40,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
u32 sdc_fifo_cfg;
};
-@@ -1747,6 +1751,9 @@ static int msdc_prepare_hs400_tuning(str
+@@ -1750,6 +1754,9 @@ static int msdc_prepare_hs400_tuning(str
writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
/* hs400 mode must set it to 0 */
sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
@@ -50,7 +50,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
return 0;
}
-@@ -1997,6 +2004,7 @@ static void msdc_save_reg(struct msdc_ho
+@@ -2000,6 +2007,7 @@ static void msdc_save_reg(struct msdc_ho
host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
@@ -58,7 +58,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
}
-@@ -2014,6 +2022,7 @@ static void msdc_restore_reg(struct msdc
+@@ -2017,6 +2025,7 @@ static void msdc_restore_reg(struct msdc
writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);