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| author | Daniel Golle <daniel@makrotopia.org> | 2022-10-09 16:34:35 +0100 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2022-10-09 16:41:16 +0100 |
| commit | 88eae0f0366d483dad77e5e4e9cdb02c99523e69 (patch) | |
| tree | b5c9a92d7b2e05255237d59facfa08a517ec3d9b /target/linux/mediatek/files-5.15 | |
| parent | 629f2de1a772bbfc6bbc37a3aacb67805dc9fb39 (diff) | |
| download | upstream-88eae0f0366d483dad77e5e4e9cdb02c99523e69.tar.gz upstream-88eae0f0366d483dad77e5e4e9cdb02c99523e69.tar.bz2 upstream-88eae0f0366d483dad77e5e4e9cdb02c99523e69.zip | |
mediatek: filogic: set correct PWM clock and clean thermal zone
* set correct clocks for PWM to work.
* MT7986 PWM does have the 26MHz-clock-select, set that in patch
* drop useless 'passive' trip point in thermal zone
* extend pwm-fan to have 3 active operating points
* set reasonable trip points in thermal zone
* invert pwm-fan operating points and set shorter period to allow
less noisy operation of the PWM fan of the BPi-R3.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/mediatek/files-5.15')
| -rw-r--r-- | target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index ade4cebbd5..be82acd204 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -206,8 +206,8 @@ #clock-cells = <1>; #pwm-cells = <2>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&infracfg CLK_INFRA_PWM_BSEL>, + clocks = <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM_STA>, <&infracfg CLK_INFRA_PWM1_CK>, <&infracfg CLK_INFRA_PWM2_CK>; clock-names = "top", "main", "pwm1", "pwm2"; @@ -664,8 +664,8 @@ fan: pwm-fan { compatible = "pwm-fan"; - /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ - cooling-levels = <0 128 255>; + /* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */ + cooling-levels = <0 86 172 255>; #cooling-cells = <2>; status = "disabled"; }; @@ -694,14 +694,14 @@ type = "active"; }; - cpu_trip_active_low: active-low { + cpu_trip_active_med: active-med { temperature = <85000>; hysteresis = <2000>; type = "active"; }; - cpu_trip_passive: passive { - temperature = <40000>; + cpu_trip_active_low: active-low { + temperature = <60000>; hysteresis = <2000>; type = "passive"; }; @@ -709,24 +709,23 @@ cooling-maps { cpu-active-high { + /* active: set fan to cooling level 3 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-med { /* active: set fan to cooling level 2 */ cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_high>; + trip = <&cpu_trip_active_med>; }; cpu-active-low { - /* active: set fan to cooling level 1 */ + /* passive: set fan to cooling level 1 */ cooling-device = <&fan 1 1>; trip = <&cpu_trip_active_low>; }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; }; - }; }; }; |