diff options
| author | Daniel Golle <daniel@makrotopia.org> | 2023-06-04 15:56:15 +0100 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2023-06-09 19:23:03 +0100 |
| commit | a65ec9fea7c9bf0ed2c247e37448f4189b01adf2 (patch) | |
| tree | 2b8c0210ff203204a5b1d2acbf9f1a2e9106abf8 /target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h | |
| parent | bca04036ffc9fd6f891eafb7996510dce9af0fbc (diff) | |
| download | upstream-a65ec9fea7c9bf0ed2c247e37448f4189b01adf2.tar.gz upstream-a65ec9fea7c9bf0ed2c247e37448f4189b01adf2.tar.bz2 upstream-a65ec9fea7c9bf0ed2c247e37448f4189b01adf2.zip | |
mediatek: sync MT7986 device trees with upstream
Sync device tree files for MT7986 boards with what landed in upstream
Linux tree to easy maintainance and also allow for a smooth update to
Linux 6.1.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 7a0ec001ff79b12beefb8f3773820bfedebbb340)
Diffstat (limited to 'target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h')
| -rw-r--r-- | target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h | 59 |
1 files changed, 52 insertions, 7 deletions
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h b/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h index 1bdfe34a7a..af3d16c811 100644 --- a/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h +++ b/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h @@ -1,10 +1,55 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2021 MediaTek Inc. */ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ -#ifndef _DT_BINDINGS_RESET_MT7986 -#define _DT_BINDINGS_RESET_MT7986 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 +#define _DT_BINDINGS_RESET_CONTROLLER_MT7986 -#define MT7986_TOPRGU_CONSYS_RST 23 -#define MT7986_TOPRGU_SW_RST_NUM 32 +/* INFRACFG resets */ +#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 +#define MT7986_INFRACFG_SSUSB_SW_RST 7 +#define MT7986_INFRACFG_EIP97_SW_RST 8 +#define MT7986_INFRACFG_AUDIO_SW_RST 13 +#define MT7986_INFRACFG_CQ_DMA_SW_RST 14 -#endif /* _DT_BINDINGS_RESET_MT7986 */ +#define MT7986_INFRACFG_TRNG_SW_RST 17 +#define MT7986_INFRACFG_AP_DMA_SW_RST 32 +#define MT7986_INFRACFG_I2C_SW_RST 33 +#define MT7986_INFRACFG_NFI_SW_RST 34 +#define MT7986_INFRACFG_SPI0_SW_RST 35 +#define MT7986_INFRACFG_SPI1_SW_RST 36 +#define MT7986_INFRACFG_UART0_SW_RST 37 +#define MT7986_INFRACFG_UART1_SW_RST 38 +#define MT7986_INFRACFG_UART2_SW_RST 39 +#define MT7986_INFRACFG_AUXADC_SW_RST 43 + +#define MT7986_INFRACFG_APXGPT_SW_RST 66 +#define MT7986_INFRACFG_PWM_SW_RST 68 + +#define MT7986_INFRACFG_SW_RST_NUM 69 + +/* TOPRGU resets */ +#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 +#define MT7986_TOPRGU_SGMII0_SW_RST 1 +#define MT7986_TOPRGU_SGMII1_SW_RST 2 +#define MT7986_TOPRGU_INFRA_SW_RST 3 +#define MT7986_TOPRGU_U2PHY_SW_RST 5 +#define MT7986_TOPRGU_PCIE_SW_RST 6 +#define MT7986_TOPRGU_SSUSB_SW_RST 7 +#define MT7986_TOPRGU_ETHDMA_SW_RST 20 +#define MT7986_TOPRGU_CONSYS_SW_RST 23 + +#define MT7986_TOPRGU_SW_RST_NUM 24 + +/* ETHSYS Subsystem resets */ +#define MT7986_ETHSYS_FE_SW_RST 6 +#define MT7986_ETHSYS_PMTR_SW_RST 8 +#define MT7986_ETHSYS_GMAC_SW_RST 23 +#define MT7986_ETHSYS_PPE0_SW_RST 30 +#define MT7986_ETHSYS_PPE1_SW_RST 31 + +#define MT7986_ETHSYS_SW_RST_NUM 32 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */ |