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| author | Daniel Golle <daniel@makrotopia.org> | 2022-10-20 20:20:41 +0100 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2022-10-20 20:37:50 +0100 |
| commit | c15e7e291072b90cc23884d25f0462bc358e8e4a (patch) | |
| tree | beddb869fa71394ed6f35984814c5ad4d86c999b /target/linux/mediatek/files-5.15/arch/arm64/boot | |
| parent | a53f29b583dd974b8b65737bab7fbca7753c738c (diff) | |
| download | upstream-c15e7e291072b90cc23884d25f0462bc358e8e4a.tar.gz upstream-c15e7e291072b90cc23884d25f0462bc358e8e4a.tar.bz2 upstream-c15e7e291072b90cc23884d25f0462bc358e8e4a.zip | |
mediatek: filogic: consolidate adc '32k' clock
Add dependency to '32k' ADC clock so it is always enabled for thermal
and raw access to ADC values. This allows to remove the patch for the
ADC driver and reduce the patch adding thermal support for MT7986 to
only add the new efuse layout and temperature decoding for V3.
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/mediatek/files-5.15/arch/arm64/boot')
| -rw-r--r-- | target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index be82acd204..060b88f9dd 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -297,9 +297,8 @@ compatible = "mediatek,mt7986-auxadc", "mediatek,mt7622-auxadc"; reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "main", "32k"; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "main"; #io-channel-cells = <1>; }; @@ -349,9 +348,8 @@ reg = <0 0x1100c800 0 0x800>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "therm", "auxadc", "adc_32k"; + <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "therm", "auxadc"; mediatek,auxadc = <&auxadc>; mediatek,apmixedsys = <&apmixedsys>; nvmem-cells = <&thermal_calibration>; |