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author | Florian Fainelli <florian@openwrt.org> | 2012-11-13 17:39:44 +0000 |
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committer | Florian Fainelli <florian@openwrt.org> | 2012-11-13 17:39:44 +0000 |
commit | e7f77f27421866c3dd9798f7784a4d9b0ab0c368 (patch) | |
tree | 5a8920f9d98a888b0ef42165db6c162804e9a820 /target/linux/malta/patches-3.6/002-MIPS-Malta-fix-build-failure.patch | |
parent | 857456aef8d10b5c67f49542018237acf4fc0e2b (diff) | |
download | upstream-e7f77f27421866c3dd9798f7784a4d9b0ab0c368.tar.gz upstream-e7f77f27421866c3dd9798f7784a4d9b0ab0c368.tar.bz2 upstream-e7f77f27421866c3dd9798f7784a4d9b0ab0c368.zip |
fix badly named patch file
SVN-Revision: 34193
Diffstat (limited to 'target/linux/malta/patches-3.6/002-MIPS-Malta-fix-build-failure.patch')
-rw-r--r-- | target/linux/malta/patches-3.6/002-MIPS-Malta-fix-build-failure.patch | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/target/linux/malta/patches-3.6/002-MIPS-Malta-fix-build-failure.patch b/target/linux/malta/patches-3.6/002-MIPS-Malta-fix-build-failure.patch new file mode 100644 index 0000000000..f14cdb2d8e --- /dev/null +++ b/target/linux/malta/patches-3.6/002-MIPS-Malta-fix-build-failure.patch @@ -0,0 +1,28 @@ +From 4ade440f81a3c248068d8b89eea7754cc8705b58 Mon Sep 17 00:00:00 2001 +From: Ralf Baechle <ralf@linux-mips.org> +Date: Tue, 13 Nov 2012 14:33:30 +0100 +Subject: [PATCH] MIPS: Malta: Fix build error + +Caused by fe2ccd4dcebd3c5e264af1705bb9b659972418cc [MIPS: Malta: Fix +interupt number of CBUS UART.] + +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/mti-malta/malta-platform.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c +index c154181..7473217 100644 +--- a/arch/mips/mti-malta/malta-platform.c ++++ b/arch/mips/mti-malta/malta-platform.c +@@ -29,6 +29,7 @@ + #include <linux/mtd/partitions.h> + #include <linux/mtd/physmap.h> + #include <linux/platform_device.h> ++#include <asm/mips-boards/maltaint.h> + #include <mtd/mtd-abi.h> + + #define SMC_PORT(base, int) \ +-- +1.7.11.7 + |