aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/malta/be64
diff options
context:
space:
mode:
authorFlorian Fainelli <florian@openwrt.org>2013-04-05 12:36:48 +0000
committerFlorian Fainelli <florian@openwrt.org>2013-04-05 12:36:48 +0000
commit495296bba9055cfffcf849228e1b6504cc9bdf34 (patch)
tree435e618367994e3b98162f81834d78066d3be0fc /target/linux/malta/be64
parent12b925dcbf63591db32c44523b81dad20b46e9a6 (diff)
downloadupstream-495296bba9055cfffcf849228e1b6504cc9bdf34.tar.gz
upstream-495296bba9055cfffcf849228e1b6504cc9bdf34.tar.bz2
upstream-495296bba9055cfffcf849228e1b6504cc9bdf34.zip
malta: add le64 and be64 sub targets
These two subtargets are used to build a 64-bit malta kernel along with 64-bit userland support. Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 36211
Diffstat (limited to 'target/linux/malta/be64')
-rw-r--r--target/linux/malta/be64/config-default14
-rw-r--r--target/linux/malta/be64/target.mk11
2 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/malta/be64/config-default b/target/linux/malta/be64/config-default
new file mode 100644
index 0000000000..6caac8aac1
--- /dev/null
+++ b/target/linux/malta/be64/config-default
@@ -0,0 +1,14 @@
+CONFIG_64BIT=y
+# CONFIG_32BIT is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+# CONFIG_HUGETLBFS is not set
+CONFIG_CPU_BIG_ENDIAN=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPS64_R1=y
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
diff --git a/target/linux/malta/be64/target.mk b/target/linux/malta/be64/target.mk
new file mode 100644
index 0000000000..30804f4e1e
--- /dev/null
+++ b/target/linux/malta/be64/target.mk
@@ -0,0 +1,11 @@
+ARCH:=mips64
+ARCH_PACKAGES:=malta_mips64
+SUBTARGET:=be64
+BOARDNAME:=Big Endian (64-bits)
+CFLAGS:=-Os -pipe -mips64 -mtune=mips64 -fno-caller-saves
+FEATURES:=ramdisk
+
+define Target/Description
+ Build BE firmware images for MIPS Malta CoreLV board running in
+ big-endian and 64-bits mode
+endef