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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2022-04-06 00:46:27 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2022-04-07 20:42:34 +0200 |
| commit | 39bf2aee0ed840ff6bb4838bc0a42aaddc36a4d3 (patch) | |
| tree | 1af94a9d02252f72613b12dcbdeebd6cb6ffc04d /target/linux/layerscape/patches-5.4 | |
| parent | 3008f1f441a41e162311cee1ccadfdaaec1581c1 (diff) | |
| download | upstream-39bf2aee0ed840ff6bb4838bc0a42aaddc36a4d3.tar.gz upstream-39bf2aee0ed840ff6bb4838bc0a42aaddc36a4d3.tar.bz2 upstream-39bf2aee0ed840ff6bb4838bc0a42aaddc36a4d3.zip | |
kernel: bump 5.4 to 5.4.188
Added the new configuration options:
CONFIG_HARDEN_BRANCH_HISTORY=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
Manually adapted:
target/linux/generic/hack-5.4/220-gc_sections.patch
Compile-tested: lantiq/xrx200, armvirt/64
Run-tested: lantiq/xrx200, armvirt/64
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/layerscape/patches-5.4')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/301-arch-0008-arm-add-new-non-shareable-ioremap.patch | 6 | ||||
| -rw-r--r-- | target/linux/layerscape/patches-5.4/814-qe-0005-QE-remove-PPCisms-for-QE.patch | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/target/linux/layerscape/patches-5.4/301-arch-0008-arm-add-new-non-shareable-ioremap.patch b/target/linux/layerscape/patches-5.4/301-arch-0008-arm-add-new-non-shareable-ioremap.patch index c09efca570..e2da01fb0f 100644 --- a/target/linux/layerscape/patches-5.4/301-arch-0008-arm-add-new-non-shareable-ioremap.patch +++ b/target/linux/layerscape/patches-5.4/301-arch-0008-arm-add-new-non-shareable-ioremap.patch @@ -63,7 +63,7 @@ Signed-off-by: Roy Pledge <roy.pledge@nxp.com> * address space as memory. Needed when the kernel wants to execute --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c -@@ -314,6 +314,13 @@ static struct mem_type mem_types[] __ro_ +@@ -316,6 +316,13 @@ static struct mem_type mem_types[] __ro_ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, @@ -77,7 +77,7 @@ Signed-off-by: Roy Pledge <roy.pledge@nxp.com> [MT_ROM] = { .prot_sect = PMD_TYPE_SECT, .domain = DOMAIN_KERNEL, -@@ -650,6 +657,7 @@ static void __init build_mem_type_table( +@@ -652,6 +659,7 @@ static void __init build_mem_type_table( } kern_pgprot |= PTE_EXT_AF; vecs_pgprot |= PTE_EXT_AF; @@ -85,7 +85,7 @@ Signed-off-by: Roy Pledge <roy.pledge@nxp.com> /* * Set PXN for user mappings -@@ -678,6 +686,7 @@ static void __init build_mem_type_table( +@@ -680,6 +688,7 @@ static void __init build_mem_type_table( mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; diff --git a/target/linux/layerscape/patches-5.4/814-qe-0005-QE-remove-PPCisms-for-QE.patch b/target/linux/layerscape/patches-5.4/814-qe-0005-QE-remove-PPCisms-for-QE.patch index 496cd3cacf..1d83b124d8 100644 --- a/target/linux/layerscape/patches-5.4/814-qe-0005-QE-remove-PPCisms-for-QE.patch +++ b/target/linux/layerscape/patches-5.4/814-qe-0005-QE-remove-PPCisms-for-QE.patch @@ -210,7 +210,7 @@ Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> #undef DEBUG -@@ -57,16 +55,16 @@ void __par_io_config_pin(struct qe_pio_r +@@ -59,16 +57,16 @@ void __par_io_config_pin(struct qe_pio_r pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); /* Set open drain, if required */ @@ -232,7 +232,7 @@ Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> /* get all bits mask for 2 bit per port */ pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - -@@ -78,34 +76,30 @@ void __par_io_config_pin(struct qe_pio_r +@@ -80,34 +78,30 @@ void __par_io_config_pin(struct qe_pio_r /* clear and set 2 bits mask */ if (pin > (QE_PIO_PINS / 2) - 1) { @@ -277,7 +277,7 @@ Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> } } EXPORT_SYMBOL(__par_io_config_pin); -@@ -133,12 +127,12 @@ int par_io_data_set(u8 port, u8 pin, u8 +@@ -135,12 +129,12 @@ int par_io_data_set(u8 port, u8 pin, u8 /* calculate pin location */ pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); |