kernel: delete Linux 5.4 config and patches

As the upcoming release will be based on Linux 5.10 only, remove all
kernel configuration as well as patches for Linux 5.4.
There were no targets still actively using Linux 5.4.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 3a14580411adfb75f9a44eded9f41245b9e44606)

1 files changed, 0 insertions, 286 deletions

diff --git a/target/linux/layerscape/patches-5.4/812-pcie-0008-Revert-PCI-mobiveil-Fix-csr_read-write-build-issue.patch b/target/linux/layerscape/patches-5.4/812-pcie-0008-Revert-PCI-mobiveil-Fix-csr_read-write-build-issue.patch
deleted file mode 100644
index f6ac0c467d..0000000000
--- a/target/linux/layerscape/patches-5.4/812-pcie-0008-Revert-PCI-mobiveil-Fix-csr_read-write-build-issue.patch
+++ /dev/null
@@ -1,286 +0,0 @@
-From c3f16eeaa68f3be291dd62efadeb733d6d40279a Mon Sep 17 00:00:00 2001
-From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Tue, 18 Feb 2020 09:13:00 +0800
-Subject: [PATCH] Revert "PCI: mobiveil: Fix csr_read()/write() build issue"
-
-This reverts commit 1865d6440fb63ad979d7034b2d7c94937bfd2200.
-
-PCI: mobiveil: Fix csr_read()/write() build issue
-
-[ Upstream commit 4906c05b87d44c19b225935e24d62e4480ca556d ]
----
- drivers/pci/controller/pcie-mobiveil.c | 119 ++++++++++++++++-----------------
- 1 file changed, 57 insertions(+), 62 deletions(-)
-
---- a/drivers/pci/controller/pcie-mobiveil.c
-+++ b/drivers/pci/controller/pcie-mobiveil.c
-@@ -235,7 +235,7 @@ static int mobiveil_pcie_write(void __io
- 	return PCIBIOS_SUCCESSFUL;
- }
- 
--static u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
-+static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
- {
- 	void *addr;
- 	u32 val;
-@@ -250,8 +250,7 @@ static u32 mobiveil_csr_read(struct mobi
- 	return val;
- }
- 
--static void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
--			       size_t size)
-+static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
- {
- 	void *addr;
- 	int ret;
-@@ -263,19 +262,19 @@ static void mobiveil_csr_write(struct mo
- 		dev_err(&pcie->pdev->dev, "write CSR address failed\n");
- }
- 
--static u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
-+static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
- {
--	return mobiveil_csr_read(pcie, off, 0x4);
-+	return csr_read(pcie, off, 0x4);
- }
- 
--static void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
-+static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
- {
--	mobiveil_csr_write(pcie, val, off, 0x4);
-+	csr_write(pcie, val, off, 0x4);
- }
- 
- static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
- {
--	return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
-+	return (csr_readl(pcie, LTSSM_STATUS) &
- 		LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
- }
- 
-@@ -324,7 +323,7 @@ static void __iomem *mobiveil_pcie_map_b
- 		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
- 		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
- 
--	mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
-+	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
- 
- 	return pcie->config_axi_slave_base + where;
- }
-@@ -354,14 +353,13 @@ static void mobiveil_pcie_isr(struct irq
- 	chained_irq_enter(chip, desc);
- 
- 	/* read INTx status */
--	val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
--	mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
-+	val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
-+	mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
- 	intr_status = val & mask;
- 
- 	/* Handle INTx */
- 	if (intr_status & PAB_INTP_INTX_MASK) {
--		shifted_status = mobiveil_csr_readl(pcie,
--						    PAB_INTP_AMBA_MISC_STAT);
-+		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
- 		shifted_status &= PAB_INTP_INTX_MASK;
- 		shifted_status >>= PAB_INTX_START;
- 		do {
-@@ -375,13 +373,12 @@ static void mobiveil_pcie_isr(struct irq
- 							    bit);
- 
- 				/* clear interrupt handled */
--				mobiveil_csr_writel(pcie,
--						    1 << (PAB_INTX_START + bit),
--						    PAB_INTP_AMBA_MISC_STAT);
-+				csr_writel(pcie, 1 << (PAB_INTX_START + bit),
-+					   PAB_INTP_AMBA_MISC_STAT);
- 			}
- 
--			shifted_status = mobiveil_csr_readl(pcie,
--							    PAB_INTP_AMBA_MISC_STAT);
-+			shifted_status = csr_readl(pcie,
-+						   PAB_INTP_AMBA_MISC_STAT);
- 			shifted_status &= PAB_INTP_INTX_MASK;
- 			shifted_status >>= PAB_INTX_START;
- 		} while (shifted_status != 0);
-@@ -416,7 +413,7 @@ static void mobiveil_pcie_isr(struct irq
- 	}
- 
- 	/* Clear the interrupt status */
--	mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
-+	csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
- 	chained_irq_exit(chip, desc);
- }
- 
-@@ -477,24 +474,24 @@ static void program_ib_windows(struct mo
- 		return;
- 	}
- 
--	value = mobiveil_csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
-+	value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
- 	value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
- 	value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
- 		 (lower_32_bits(size64) & WIN_SIZE_MASK);
--	mobiveil_csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
-+	csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
- 
--	mobiveil_csr_writel(pcie, upper_32_bits(size64),
--			    PAB_EXT_PEX_AMAP_SIZEN(win_num));
-+	csr_writel(pcie, upper_32_bits(size64),
-+		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
- 
--	mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr),
--			    PAB_PEX_AMAP_AXI_WIN(win_num));
--	mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
--			    PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
--
--	mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
--			    PAB_PEX_AMAP_PEX_WIN_L(win_num));
--	mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
--			    PAB_PEX_AMAP_PEX_WIN_H(win_num));
-+	csr_writel(pcie, lower_32_bits(cpu_addr),
-+		   PAB_PEX_AMAP_AXI_WIN(win_num));
-+	csr_writel(pcie, upper_32_bits(cpu_addr),
-+		   PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
-+
-+	csr_writel(pcie, lower_32_bits(pci_addr),
-+		   PAB_PEX_AMAP_PEX_WIN_L(win_num));
-+	csr_writel(pcie, upper_32_bits(pci_addr),
-+		   PAB_PEX_AMAP_PEX_WIN_H(win_num));
- 
- 	pcie->ib_wins_configured++;
- }
-@@ -518,29 +515,27 @@ static void program_ob_windows(struct mo
- 	 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
- 	 * to 4 KB in PAB_AXI_AMAP_CTRL register
- 	 */
--	value = mobiveil_csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
-+	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
- 	value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
- 	value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
- 		 (lower_32_bits(size64) & WIN_SIZE_MASK);
--	mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
-+	csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
- 
--	mobiveil_csr_writel(pcie, upper_32_bits(size64),
--			    PAB_EXT_AXI_AMAP_SIZE(win_num));
-+	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
- 
- 	/*
- 	 * program AXI window base with appropriate value in
- 	 * PAB_AXI_AMAP_AXI_WIN0 register
- 	 */
--	mobiveil_csr_writel(pcie,
--			    lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
--			    PAB_AXI_AMAP_AXI_WIN(win_num));
--	mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
--			    PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
--
--	mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
--			    PAB_AXI_AMAP_PEX_WIN_L(win_num));
--	mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
--			    PAB_AXI_AMAP_PEX_WIN_H(win_num));
-+	csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
-+		   PAB_AXI_AMAP_AXI_WIN(win_num));
-+	csr_writel(pcie, upper_32_bits(cpu_addr),
-+		   PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
-+
-+	csr_writel(pcie, lower_32_bits(pci_addr),
-+		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
-+	csr_writel(pcie, upper_32_bits(pci_addr),
-+		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
- 
- 	pcie->ob_wins_configured++;
- }
-@@ -584,42 +579,42 @@ static int mobiveil_host_init(struct mob
- 	struct resource_entry *win;
- 
- 	/* setup bus numbers */
--	value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
-+	value = csr_readl(pcie, PCI_PRIMARY_BUS);
- 	value &= 0xff000000;
- 	value |= 0x00ff0100;
--	mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
-+	csr_writel(pcie, value, PCI_PRIMARY_BUS);
- 
- 	/*
- 	 * program Bus Master Enable Bit in Command Register in PAB Config
- 	 * Space
- 	 */
--	value = mobiveil_csr_readl(pcie, PCI_COMMAND);
-+	value = csr_readl(pcie, PCI_COMMAND);
- 	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
--	mobiveil_csr_writel(pcie, value, PCI_COMMAND);
-+	csr_writel(pcie, value, PCI_COMMAND);
- 
- 	/*
- 	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
- 	 * register
- 	 */
--	pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
-+	pab_ctrl = csr_readl(pcie, PAB_CTRL);
- 	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
--	mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
-+	csr_writel(pcie, pab_ctrl, PAB_CTRL);
- 
--	mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
--			    PAB_INTP_AMBA_MISC_ENB);
-+	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
-+		   PAB_INTP_AMBA_MISC_ENB);
- 
- 	/*
- 	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
- 	 * PAB_AXI_PIO_CTRL Register
- 	 */
--	value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
-+	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
- 	value |= APIO_EN_MASK;
--	mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
-+	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
- 
- 	/* Enable PCIe PIO master */
--	value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
-+	value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
- 	value |= 1 << PIO_ENABLE_SHIFT;
--	mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
-+	csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
- 
- 	/*
- 	 * we'll program one outbound window for config reads and
-@@ -652,10 +647,10 @@ static int mobiveil_host_init(struct mob
- 	}
- 
- 	/* fixup for PCIe class register */
--	value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
-+	value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
- 	value &= 0xff;
- 	value |= (PCI_CLASS_BRIDGE_PCI << 16);
--	mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
-+	csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
- 
- 	/* setup MSI hardware registers */
- 	mobiveil_pcie_enable_msi(pcie);
-@@ -673,9 +668,9 @@ static void mobiveil_mask_intx_irq(struc
- 	pcie = irq_desc_get_chip_data(desc);
- 	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
- 	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
--	shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
-+	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
- 	shifted_val &= ~mask;
--	mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
-+	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
- 	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
- }
- 
-@@ -689,9 +684,9 @@ static void mobiveil_unmask_intx_irq(str
- 	pcie = irq_desc_get_chip_data(desc);
- 	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
- 	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
--	shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
-+	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
- 	shifted_val |= mask;
--	mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
-+	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
- 	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
- }
-