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author | Yangbo Lu <yangbo.lu@nxp.com> | 2020-04-10 10:47:05 +0800 |
---|---|---|
committer | Petr Štetiar <ynezz@true.cz> | 2020-05-07 12:53:06 +0200 |
commit | cddd4591404fb4c53dc0b3c0b15b942cdbed4356 (patch) | |
tree | 392c1179de46b0f804e3789edca19069b64e6b44 /target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch | |
parent | d1d2c0b5579ea4f69a42246c9318539d61ba1999 (diff) | |
download | upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.tar.gz upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.tar.bz2 upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.zip |
layerscape: add patches-5.4
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/
For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.
The patches are sorted into the following categories:
301-arch-xxxx
302-dts-xxxx
303-core-xxxx
701-net-xxxx
801-audio-xxxx
802-can-xxxx
803-clock-xxxx
804-crypto-xxxx
805-display-xxxx
806-dma-xxxx
807-gpio-xxxx
808-i2c-xxxx
809-jailhouse-xxxx
810-keys-xxxx
811-kvm-xxxx
812-pcie-xxxx
813-pm-xxxx
814-qe-xxxx
815-sata-xxxx
816-sdhc-xxxx
817-spi-xxxx
818-thermal-xxxx
819-uart-xxxx
820-usb-xxxx
821-vfio-xxxx
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch')
-rw-r--r-- | target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch b/target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch new file mode 100644 index 0000000000..8cf6215e2a --- /dev/null +++ b/target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch @@ -0,0 +1,107 @@ +From 6adf87956ee1043e6bf0ef83fa0eec1e755c0d48 Mon Sep 17 00:00:00 2001 +From: Marc Kleine-Budde <mkl@pengutronix.de> +Date: Fri, 1 Mar 2019 12:17:30 +0100 +Subject: [PATCH] can: flexcan: convert struct flexcan_priv::rx_mask{1,2} to + rx_mask + +The flexcan IP core has up to 64 mailboxes, each one has a corresponding +interrupt bit in the iflag1 or iflag2 registers and a mask bit in the +imask1 or imask2 registers. + +In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX +interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of +struct flexcan_priv for this. + +This patch merges the two u32 rx_mask1 and rx_mask2 to a single u64 rx_mask +variable, which simplifies the code a bit. + +Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> +--- + drivers/net/can/flexcan.c | 30 +++++++++++++----------------- + 1 file changed, 13 insertions(+), 17 deletions(-) + +--- a/drivers/net/can/flexcan.c ++++ b/drivers/net/can/flexcan.c +@@ -142,6 +142,7 @@ + #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8 + #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0 + #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1) ++#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x) + #define FLEXCAN_IFLAG2_MB(x) BIT((x) & 0x1f) + #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) + #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) +@@ -277,9 +278,8 @@ struct flexcan_priv { + u8 mb_size; + u8 clk_src; /* clock source of CAN Protocol Engine */ + ++ u64 rx_mask; + u32 reg_ctrl_default; +- u32 rx_mask1; +- u32 rx_mask2; + + struct clk *clk_ipg; + struct clk *clk_per; +@@ -873,16 +873,15 @@ static struct sk_buff *flexcan_mailbox_r + return skb; + } + +- + static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv) + { + struct flexcan_regs __iomem *regs = priv->regs; +- u32 iflag1, iflag2; ++ u64 iflag; + +- iflag2 = priv->read(®s->iflag2) & priv->rx_mask2; +- iflag1 = priv->read(®s->iflag1) & priv->rx_mask1; ++ iflag = (u64)priv->read(®s->iflag2) << 32 | ++ priv->read(®s->iflag1); + +- return (u64)iflag2 << 32 | iflag1; ++ return iflag & priv->rx_mask; + } + + static irqreturn_t flexcan_irq(int irq, void *dev_id) +@@ -1053,6 +1052,7 @@ static int flexcan_chip_start(struct net + struct flexcan_priv *priv = netdev_priv(dev); + struct flexcan_regs __iomem *regs = priv->regs; + u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; ++ u64 reg_imask; + int err, i; + struct flexcan_mb __iomem *mb; + +@@ -1227,8 +1227,9 @@ static int flexcan_chip_start(struct net + /* enable interrupts atomically */ + disable_irq(dev->irq); + priv->write(priv->reg_ctrl_default, ®s->ctrl); +- priv->write(priv->rx_mask1, ®s->imask1); +- priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), ®s->imask2); ++ reg_imask = priv->rx_mask | FLEXCAN_IFLAG_MB(priv->tx_mb_idx); ++ priv->write(upper_32_bits(reg_imask), ®s->imask2); ++ priv->write(lower_32_bits(reg_imask), ®s->imask1); + enable_irq(dev->irq); + + /* print chip status */ +@@ -1300,19 +1301,14 @@ static int flexcan_open(struct net_devic + priv->offload.mailbox_read = flexcan_mailbox_read; + + if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { +- u64 imask; +- + priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST; + priv->offload.mb_last = priv->mb_count - 2; + +- imask = GENMASK_ULL(priv->offload.mb_last, +- priv->offload.mb_first); +- priv->rx_mask1 = imask; +- priv->rx_mask2 = imask >> 32; +- ++ priv->rx_mask = GENMASK_ULL(priv->offload.mb_last, ++ priv->offload.mb_first); + err = can_rx_offload_add_timestamp(dev, &priv->offload); + } else { +- priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | ++ priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | + FLEXCAN_IFLAG_RX_FIFO_AVAILABLE; + err = can_rx_offload_add_fifo(dev, &priv->offload, + FLEXCAN_NAPI_WEIGHT); |