layerscape: add patches-5.4

Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

1 files changed, 452 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-5.4/302-dts-0112-arm64-dts-fsl-ls1028a-prepare-dts-for-overlay.patch b/target/linux/layerscape/patches-5.4/302-dts-0112-arm64-dts-fsl-ls1028a-prepare-dts-for-overlay.patch
new file mode 100644
index 0000000000..ccadbf99bc
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/302-dts-0112-arm64-dts-fsl-ls1028a-prepare-dts-for-overlay.patch
@@ -0,0 +1,452 @@
+From a5009b362d65c24e7b2a40824e351903d75a47dc Mon Sep 17 00:00:00 2001
+From: Alex Marginean <alexandru.marginean@nxp.com>
+Date: Mon, 6 Jan 2020 16:36:44 +0200
+Subject: [PATCH] arm64: dts: fsl-ls1028a: prepare dts for overlay
+
+Named the ports node of the Felix Eth switch so it can be used in DT
+overlays to associate the ports with proper PHYs.
+Ports are now by default disabled in dtsi, so if the board dts doesn't
+do anything about them they stay disabled.
+Updated RDB and QDS dts files to match.
+Replaced all 'phy-connection-type' with 'phy-mode'.
+The set-up for protocol 7777 on QDS was changed to a single quad port card
+in slot 1.  This requires a QDS board with no lane B rework and a AQR412
+or similar PHY card without any lane rework done on it.
+
+Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
+---
+ .../boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi   | 58 ++++++++++-----------
+ .../boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi   | 59 ++++++++++------------
+ .../boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi   | 51 ++++++++++++-------
+ .../boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi   | 43 ++++++++++------
+ arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts  | 44 +++++++++-------
+ arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi     | 27 +++++++---
+ 6 files changed, 161 insertions(+), 121 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
+@@ -7,50 +7,50 @@
+  */
+ 
+ &mdio_slot1 {
+-	/* two ports on AQR412 */
+-	slot1_sxgmii2: ethernet-phy@2 {
+-		reg = <0x2>;
++	slot1_sxgmii0: ethernet-phy@0 {
++		reg = <0x0>;
+ 		compatible = "ethernet-phy-ieee802.3-c45";
+ 	};
+-	slot1_sxgmii3: ethernet-phy@3 {
+-		reg = <0x3>;
++
++	slot1_sxgmii1: ethernet-phy@1 {
++		reg = <0x1>;
+ 		compatible = "ethernet-phy-ieee802.3-c45";
+ 	};
+-};
+ 
+-&mdio_slot2 {
+-	slot2_sxgmii0: ethernet-phy@2 {
+-		/* AQR112 */
++	slot1_sxgmii2: ethernet-phy@2 {
+ 		reg = <0x2>;
+ 		compatible = "ethernet-phy-ieee802.3-c45";
+ 	};
+-};
+ 
+-&mdio_slot3 {
+-	slot3_sxgmii0: ethernet-phy@2 {
+-		/* AQR112 */
+-		reg = <0x2>;
++	slot1_sxgmii3: ethernet-phy@3 {
++		reg = <0x3>;
+ 		compatible = "ethernet-phy-ieee802.3-c45";
+ 	};
+ };
+ 
+ /* l2switch ports */
+-&switch_port0 {
+-	phy-handle = <&slot1_sxgmii2>;
+-	phy-connection-type = "2500base-x";
+-};
++&mscc_felix_ports {
++	port@0 {
++		status = "okay";
++		phy-handle = <&slot1_sxgmii0>;
++		phy-mode = "2500base-x";
++	};
+ 
+-&switch_port1 {
+-	phy-handle = <&slot2_sxgmii0>;
+-	phy-connection-type = "2500base-x";
+-};
++	port@1 {
++		status = "okay";
++		phy-handle = <&slot1_sxgmii1>;
++		phy-mode = "2500base-x";
++	};
+ 
+-&switch_port2 {
+-	phy-handle = <&slot3_sxgmii0>;
+-	phy-connection-type = "2500base-x";
+-};
++	port@2 {
++		status = "okay";
++		phy-handle = <&slot1_sxgmii2>;
++		phy-mode = "2500base-x";
++	};
+ 
+-&switch_port3 {
+-	phy-handle = <&slot1_sxgmii3>;
+-	phy-connection-type = "2500base-x";
++	port@3 {
++		status = "okay";
++		phy-handle = <&slot1_sxgmii3>;
++		phy-mode = "2500base-x";
++	};
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
+@@ -11,50 +11,47 @@
+ 	slot1_sgmii0: ethernet-phy@1c {
+ 		reg = <0x1c>;
+ 	};
++
+ 	slot1_sgmii1: ethernet-phy@1d {
+ 		reg = <0x1d>;
+ 	};
++
+ 	slot1_sgmii2: ethernet-phy@1e {
+ 		reg = <0x1e>;
+ 	};
+-	slot1_sgmii3: ethernet-phy@1f {
+-		reg = <0x1f>;
+-	};
+-};
+ 
+-&mdio_slot2 {
+-	/* VSC8234 */
+-	slot2_sgmii0: ethernet-phy@1c {
+-		reg = <0x1c>;
+-	};
+-	slot2_sgmii1: ethernet-phy@1d {
+-		reg = <0x1d>;
+-	};
+-	slot2_sgmii2: ethernet-phy@1e {
+-		reg = <0x1e>;
+-	};
+-	slot2_sgmii3: ethernet-phy@1f {
++	slot1_sgmii3: ethernet-phy@1f {
+ 		reg = <0x1f>;
+ 	};
+ };
+ 
+ /* l2switch ports */
+-&switch_port0 {
+-	phy-handle = <&slot1_sgmii0>;
+-	phy-connection-type = "sgmii";
+-};
++&mscc_felix_ports {
++	port@0 {
++		status = "okay";
++		phy-handle = <&slot1_sgmii0>;
++		phy-mode = "sgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port1 {
+-	phy-handle = <&slot2_sgmii0>;
+-	phy-connection-type = "sgmii";
+-};
++	port@1 {
++		status = "okay";
++		phy-handle = <&slot1_sgmii1>;
++		phy-mode = "sgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port2 {
+-	phy-handle = <&slot1_sgmii2>;
+-	phy-connection-type = "sgmii";
+-};
++	port@2 {
++		status = "okay";
++		phy-handle = <&slot1_sgmii2>;
++		phy-mode = "sgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port3 {
+-	phy-handle = <&slot1_sgmii3>;
+-	phy-connection-type = "sgmii";
++	port@3 {
++		status = "okay";
++		phy-handle = <&slot1_sgmii3>;
++		phy-mode = "sgmii";
++		managed = "in-band-status";
++	};
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
+@@ -8,41 +8,54 @@
+ 
+ &mdio_slot2 {
+ 	/* 4 ports on AQR412 */
+-	slot2_qsgmii0: ethernet-phy@0 {
++	slot2_qxgmii0: ethernet-phy@0 {
+ 		reg = <0x0>;
+ 		compatible = "ethernet-phy-ieee802.3-c45";
+ 	};
+-	slot2_qsgmii1: ethernet-phy@1 {
++
++	slot2_qxgmii1: ethernet-phy@1 {
+ 		reg = <0x1>;
+ 		compatible = "ethernet-phy-ieee802.3-c45";
+ 	};
+-	slot2_qsgmii2: ethernet-phy@2 {
++
++	slot2_qxgmii2: ethernet-phy@2 {
+ 		reg = <0x2>;
+ 		compatible = "ethernet-phy-ieee802.3-c45";
+ 	};
+-	slot2_qsgmii3: ethernet-phy@3 {
++
++	slot2_qxgmii3: ethernet-phy@3 {
+ 		reg = <0x3>;
+ 		compatible = "ethernet-phy-ieee802.3-c45";
+ 	};
+ };
+ 
+ /* l2switch ports */
+-&switch_port0 {
+-	phy-handle = <&slot2_qsgmii0>;
+-	phy-connection-type = "usxgmii";
+-};
++&mscc_felix_ports {
++	port@0 {
++		status = "okay";
++		phy-handle = <&slot2_qxgmii0>;
++		phy-mode = "usxgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port1 {
+-	phy-handle = <&slot2_qsgmii1>;
+-	phy-connection-type = "usxgmii";
+-};
++	port@1 {
++		status = "okay";
++		phy-handle = <&slot2_qxgmii1>;
++		phy-mode = "usxgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port2 {
+-	phy-handle = <&slot2_qsgmii2>;
+-	phy-connection-type = "usxgmii";
+-};
++	port@2 {
++		status = "okay";
++		phy-handle = <&slot2_qxgmii2>;
++		phy-mode = "usxgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port3 {
+-	phy-handle = <&slot2_qsgmii3>;
+-	phy-connection-type = "usxgmii";
++	port@3 {
++		status = "okay";
++		phy-handle = <&slot2_qxgmii3>;
++		phy-mode = "usxgmii";
++		managed = "in-band-status";
++	};
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
+@@ -11,34 +11,47 @@
+ 	slot2_qsgmii0: ethernet-phy@8 {
+ 		reg = <0x8>;
+ 	};
++
+ 	slot2_qsgmii1: ethernet-phy@9 {
+ 		reg = <0x9>;
+ 	};
++
+ 	slot2_qsgmii2: ethernet-phy@a {
+ 		reg = <0xa>;
+ 	};
++
+ 	slot2_qsgmii3: ethernet-phy@b {
+ 		reg = <0xb>;
+ 	};
+ };
+ 
+ /* l2switch ports */
+-&switch_port0 {
+-	phy-handle = <&slot2_qsgmii0>;
+-	phy-connection-type = "qsgmii";
+-};
++&mscc_felix_ports {
++	port@0 {
++		status = "okay";
++		phy-handle = <&slot2_qsgmii0>;
++		phy-mode = "qsgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port1 {
+-	phy-handle = <&slot2_qsgmii1>;
+-	phy-connection-type = "qsgmii";
+-};
++	port@1 {
++		status = "okay";
++		phy-handle = <&slot2_qsgmii1>;
++		phy-mode = "qsgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port2 {
+-	phy-handle = <&slot2_qsgmii2>;
+-	phy-connection-type = "qsgmii";
+-};
++	port@2 {
++		status = "okay";
++		phy-handle = <&slot2_qsgmii2>;
++		phy-mode = "qsgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port3 {
+-	phy-handle = <&slot2_qsgmii3>;
+-	phy-connection-type = "qsgmii";
++	port@3 {
++		status = "okay";
++		phy-handle = <&slot2_qsgmii3>;
++		phy-mode = "qsgmii";
++		managed = "in-band-status";
++	};
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+@@ -233,28 +233,34 @@
+ };
+ 
+ /* l2switch ports */
+-&switch_port0 {
+-	phy-handle = <&qsgmii_phy1>;
+-	phy-connection-type = "qsgmii";
+-	managed = "in-band-status";
+-};
++&mscc_felix_ports {
++	port@0 {
++		status = "okay";
++		phy-handle = <&qsgmii_phy1>;
++		phy-mode = "qsgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port1 {
+-	phy-handle = <&qsgmii_phy2>;
+-	phy-connection-type = "qsgmii";
+-	managed = "in-band-status";
+-};
++	port@1 {
++		status = "okay";
++		phy-handle = <&qsgmii_phy2>;
++		phy-mode = "qsgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port2 {
+-	phy-handle = <&qsgmii_phy3>;
+-	phy-connection-type = "qsgmii";
+-	managed = "in-band-status";
+-};
++	port@2 {
++		status = "okay";
++		phy-handle = <&qsgmii_phy3>;
++		phy-mode = "qsgmii";
++		managed = "in-band-status";
++	};
+ 
+-&switch_port3 {
+-	phy-handle = <&qsgmii_phy4>;
+-	phy-connection-type = "qsgmii";
+-	managed = "in-band-status";
++	port@3 {
++		status = "okay";
++		phy-handle = <&qsgmii_phy4>;
++		phy-mode = "qsgmii";
++		managed = "in-band-status";
++	};
+ };
+ 
+ &sai4 {
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+@@ -774,30 +774,39 @@
+ 				clocks = <&clockgen 4 0>;
+ 				little-endian;
+ 			};
+-			switch@0,5 {
++
++			ethernet-switch@0,5 {
+ 				reg = <0x000500 0 0 0 0>;
+ 				/* IEP INT_B */
+ 				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ 
+-				ports {
++				mscc_felix_ports: ports {
+ 					#address-cells = <1>;
+ 					#size-cells = <0>;
+ 
+ 					/* external ports */
+-					switch_port0: port@0 {
++					mscc_felix_port0: port@0 {
+ 						reg = <0>;
++						status = "disabled";
+ 					};
+-					switch_port1: port@1 {
++
++					mscc_felix_port1: port@1 {
+ 						reg = <1>;
++						status = "disabled";
+ 					};
+-					switch_port2: port@2 {
++
++					mscc_felix_port2: port@2 {
+ 						reg = <2>;
++						status = "disabled";
+ 					};
+-					switch_port3: port@3 {
++
++					mscc_felix_port3: port@3 {
+ 						reg = <3>;
++						status = "disabled";
+ 					};
++
+ 					/* internal to-cpu ports */
+-					port@4 {
++					mscc_felix_port4: port@4 {
+ 						reg = <4>;
+ 						ethernet = <&enetc_port2>;
+ 						phy-mode = "gmii";
+@@ -807,7 +816,8 @@
+ 							full-duplex;
+ 						};
+ 					};
+-					port@5 {
++
++					mscc_felix_port5: port@5 {
+ 						reg = <5>;
+ 						phy-mode = "gmii";
+ 						status = "disabled";
+@@ -819,6 +829,7 @@
+ 					};
+ 				};
+ 			};
++
+ 			enetc_port3: ethernet@0,6 {
+ 				compatible = "fsl,enetc";
+ 				reg = <0x000600 0 0 0 0>;