kernel: delete Linux 5.4 config and patches

As the upcoming release will be based on Linux 5.10 only, remove all
kernel configuration as well as patches for Linux 5.4.
There were no targets still actively using Linux 5.4.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

1 files changed, 0 insertions, 959 deletions

diff --git a/target/linux/layerscape/patches-5.4/302-dts-0010-arm64-dts-ls208xa-accumulated-change-to-ls208xa-boar.patch b/target/linux/layerscape/patches-5.4/302-dts-0010-arm64-dts-ls208xa-accumulated-change-to-ls208xa-boar.patch
deleted file mode 100644
index a763e05724..0000000000
--- a/target/linux/layerscape/patches-5.4/302-dts-0010-arm64-dts-ls208xa-accumulated-change-to-ls208xa-boar.patch
+++ /dev/null
@@ -1,959 +0,0 @@
-From 9d8de47b617baa4fa92d9a1502904c0373f80384 Mon Sep 17 00:00:00 2001
-From: Li Yang <leoyang.li@nxp.com>
-Date: Thu, 2 May 2019 16:12:40 -0500
-Subject: [PATCH] arm64: dts: ls208xa: accumulated change to ls208xa boards
-
-commit 46123df3a174f0d76c8b954a0386e64841453836
-Author: Florinel Iordache <florinel.iordache@nxp.com>
-Date:   Thu Aug 9 12:29:18 2018 +0300
-
-    arm64: dts: updates for Unified Backplane driver
-
-    Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
-
-commit 76a741dbb9b93ea9ab2f6122b8df5bc4f0db7676
-Author: Nipun Gupta <nipun.gupta@nxp.com>
-Date:   Sat Apr 28 00:20:16 2018 +0530
-
-    arm64: dts: ls208x: add dma-cohernet property in fsl-mc node
-
-    Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-
-commit f6309e9dc8e0c6171a43fd6759123b5de1c574aa
-Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Date:   Mon Apr 2 16:27:23 2018 +0800
-
-    arm64: dts: ls208xa: add dts entry for A-010650
-
-    Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-
-commit 8c37bad2038a210a4f0a369fd946aaae4317eac4
-Author: Nipun Gupta <nipun.gupta@nxp.com>
-Date:   Fri Apr 20 17:14:10 2018 +0530
-
-    arm64: dts: ls208x: add dma ranges property
-
-    Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-
-commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
-Author: Changming Huang <jerry.huang@nxp.com>
-Date:   Wed Apr 19 12:49:50 2017 +0800
-
-    arm/arm64: dts: Add property snps incr burst type adjustment for
-INCR burst type for dwc3
-
-    Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
-    Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
-
-commit dbb65ea8ee1d46067e756c6d64c7fe66a0058f49
-Author: Pankaj Bansal <pankaj.bansal@nxp.com>
-Date:   Mon Mar 5 12:37:04 2018 +0530
-
-    arm64: dts: ls208x: remove NXP Erratum A008585 from LS2088A.
-
-    NXP Erratum A008585 affects A57 core cluster used in LS2085rev1.
-    However this problem has been fixed in A72 core cluster used in
-LS2088.
-    Therefore remove the erratum from LS2088A. Keeping it only in
-LS2085.
-
-    Cc: <stable@vger.kernel.org> # 4.14
-    Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
-    Reviewed-by: Sandeep Malik <sandeep.malik@nxp.com>
-    Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
-
-commit 85f41b0f6abe6b9d7d303790bb3712ed559890e9
-Author: Nipun Gupta <nipun.gupta@nxp.com>
-Date:   Mon Feb 26 10:39:54 2018 +0530
-
-    arm64: dts: ls208xa: add dma coherent property in smmu node
-
-    Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-
-commit e910d8b78b823a625451b1da7ae7499dadde2ae9
-Author: Suresh Gupta <suresh.gupta@nxp.com>
-Date:   Thu Feb 1 23:49:56 2018 +0530
-
-    arm64: dts: freescale: ls208xa: Modify DT nodes for qspi
-
-    Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
-
-commit 7654ef78c8c85de3a43dfa0dffd572d589ea1332
-Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Date:   Wed Nov 1 10:34:04 2017 +0800
-
-    arm64: dts: ls208xa: correct the i2c clock to 1/2 platform pll
-
-    Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-
-commit efdb129228baa6a999c06072338b979d783d7b60
-Author: Bharat Bhushan <Bharat.Bhushan@nxp.com>
-Date:   Thu Aug 31 14:45:02 2017 +0530
-
-    arm64: dts: ls208xa: Add iommu-map property for pci
-
-    This patch adds iommu-map property for PCIe, which enables
-    SMMU for these devices on LS208xA devices.
-
-    Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
-
-commit 45af5d025eafaf4a85000e16e5f47992de663ff6
-Author: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
-Date:   Mon Aug 21 11:46:59 2017 +0300
-
-    arm64: dts: ls2088a: update backplane support with dpmac connections
-
-    Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
-
-commit b2ede6c088a883fceb348e8659253b2c7cdeeff8
-Author: Santan Kumar <santan.kumar@nxp.com>
-Date:   Thu Jun 22 13:04:00 2017 +0530
-
-    arm64: dts: ls2088ardb: Update nodes for QSPI
-
-    -As per board design, different QSPI flash is connected on
-      boards, hence change QSPI flash node from s25fl256s1 to s25fs512ss
-in
-      device tree.
-    -Enable fast-read support in QSPI node.
-
-    Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
-
-commit d5324a75c56e9f9210113e51cffa846a86b50fbd
-Author: Santan Kumar <santan.kumar@nxp.com>
-Date:   Mon Jun 19 15:26:03 2017 +0530
-
-    arm64: dts: ls2081ardb: Update nodes for QSPI, SATA, INA220
-
-    Update ls2081ardb.dts for below nodes:
-     -As per updated board design, different QSPI flash is connected on
-      boards, hence change QSPI flash node from n25q512a to s25fs512ss
-in
-      device tree.
-     -Enable dual flash support in QSPI node.
-     -Add DTS node for INA220.
-     -Enable SATA node.
-
-    Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
-    Signed-off-by: Tao Yang <b31903@freescale.com>
-    Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
-
-commit 43d506fa19e1e50e4c2e4f9689ad3c60d9a06d71
-Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Date:   Thu May 11 08:42:19 2017 +0800
-
-    arm64: dts: ls208x: add property for PCA954x Mux device
-
-    PCA954x Mux device should never be turned-off after power-on. if
-    device tree contians "i2c-mux-never-disable" property for pca954x
-    device node, it can ensure that skip disabling PCA954x Mux device.
-
-    Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-
-commit 6d3a96446a7ffccb0b9936b616d855c8d5572bce
-Author: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-Date:   Wed May 3 14:26:35 2017 +0000
-
-    arm64: dts: fsl/ls1088,ls208x: Add mdio and phy nodes
-
-    Add mdio and phy nodes for the following FSL platforms:
-    - LS1088A RDB
-    - LS2080A QDS & RDB
-    - LS2088A QDS, RDB & simu
-
-    Contains contributions from patches by the following authors:
-    Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
-    Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
-    Signed-off-by: Pratiyush Mohan Srivastava
-<pratiyush.srivastava@nxp.com>
-    Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
-    Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
-    Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
-    Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
-    Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
-    Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-    Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-
-commit 0443625ea24bc4ea315c30b718712254c588bd18
-Author: Suresh Gupta <suresh.gupta@nxp.com>
-Date:   Fri May 5 13:54:22 2017 +0530
-
-    arm64: dts: ls208xa: Add QSPI Flash node for RDB
-
-    This is temporary patch, will rewrite for open source
-
-    Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
-
-commit ed0ce1d49aa72d12ea54f82d3771a377c68af37e
-Author: Priyanka Jain <priyanka.jain@nxp.com>
-Date:   Thu Apr 13 16:49:40 2017 +0530
-
-    arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDB
-
-    This patch add support for NXP LS2081ARDB board which has
-    LS2081A SoC.
-
-    LS2081A SoC is 40-pin derivative of LS2088A SoC
-    So, from functional perspective both are same.
-    Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
-
-    Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
-
-commit e4fb842554a5e7b8c3f6e3c243222dbe4515aee3
-Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Date:   Thu Apr 27 15:01:54 2017 +0800
-
-    arm64: dts: ls208xa: add ftm0 nodes
-
-    Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-
-commit 64c3e2c3a7ddc89c3c23c012ee364f2c014524d2
-Author: costi <constantin.tudor@freescale.com>
-Date:   Fri Mar 3 18:08:28 2017 +0200
-
-    arm64: dts: fsl-ls2088: Add mdio/phy devices
-
-    Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
-
-commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
-Author: Po Liu <po.liu@nxp.com>
-Date:   Fri Sep 30 17:11:36 2016 +0800
-
-    arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
-
-    Some platforms(NXP Layerscape for example) aer/pme interrupts was
-not
-    MSI/MSI-X/INTx but using interrupt line independently. This patch
-    add "aer", "pme" interrupt-names for aer/pme interrupt.
-
-    With the interrupt-names "aer", "pme" code could probe aer/pme
-interrupt
-    line for pcie root port, replace the aer/pme interrupt service irqs.
-
-    This is intend to fixup the Layerscape platforms which aer/pmes
-interrupts
-    was not MSI/MSI-X/INTx, but using interrupt line independently.
-
-    Since the interrupt-names "intr" never been used. Remove it.
-
-    Signed-off-by: Po Liu <po.liu@nxp.com>
-    Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-
-commit 64d859836d3d194e8bc926bb951fd21859689824
-Author: Nipun Gupta <nipun.gupta@nxp.com>
-Date:   Mon Dec 5 05:20:51 2016 +0530
-
-    arm64: dts: ls208xa: Comply with the new iommu binding for fsl_mc
-
-    fsl-mc bus support the new iommu-map property. Comply to this
-binding
-    for fsl_mc bus.
-
-    Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
----
- arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts  |  62 +++++++++
- arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts  |  80 +++++++++++
- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi     |  12 ++
- arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts  | 120 ++++++++++++++++
- arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts  |  80 +++++++++++
- arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi |   1 +
- arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi |  11 +-
- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi     | 155 +++++++++++++++++++--
- 8 files changed, 505 insertions(+), 16 deletions(-)
-
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
-@@ -23,3 +23,65 @@
- 		stdout-path = "serial0:115200n8";
- 	};
- };
-+
-+&ifc {
-+	boardctrl: board-control@3,0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
-+		reg = <3 0 0x300>;		/* TODO check address */
-+		ranges = <0 3 0 0x300>;
-+
-+		mdio_mux_emi1 {
-+			compatible = "mdio-mux-mmioreg", "mdio-mux";
-+			mdio-parent-bus = <&emdio1>;
-+			reg = <0x54 1>;		/* BRDCFG4 */
-+			mux-mask = <0xe0>;	/* EMI1_MDIO */
-+
-+			#address-cells=<1>;
-+			#size-cells = <0>;
-+
-+			/* Child MDIO buses, one for each riser card:
-+			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
-+			 * VSC8234 PHYs on the riser cards.
-+			 */
-+
-+			mdio_mux3: mdio@60 {
-+				reg = <0x60>;
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				mdio0_phy12: mdio_phy0@1c {
-+					reg = <0x1c>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy13: mdio_phy1@1d {
-+					reg = <0x1d>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy14: mdio_phy2@1e {
-+					reg = <0x1e>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy15: mdio_phy3@1f {
-+					reg = <0x1f>;
-+					phy-connection-type = "sgmii";
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
-+&dpmac9 {
-+	phy-handle = <&mdio0_phy12>;
-+};
-+&dpmac10 {
-+	phy-handle = <&mdio0_phy13>;
-+};
-+&dpmac11 {
-+	phy-handle = <&mdio0_phy14>;
-+};
-+&dpmac12 {
-+	phy-handle = <&mdio0_phy15>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
-@@ -23,3 +23,83 @@
- 		stdout-path = "serial1:115200n8";
- 	};
- };
-+
-+&emdio1 {
-+	status = "disabled";
-+	/* CS4340 PHYs */
-+	mdio1_phy1: emdio1_phy@1 {
-+		reg = <0x10>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy2: emdio1_phy@2 {
-+		reg = <0x11>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy3: emdio1_phy@3 {
-+		reg = <0x12>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy4: emdio1_phy@4 {
-+		reg = <0x13>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+&emdio2 {
-+	/* AQR405 PHYs */
-+	mdio2_phy1: emdio2_phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 1 0x4>; /* Level high type */
-+		reg = <0x0>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy2: emdio2_phy@2 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 2 0x4>; /* Level high type */
-+		reg = <0x1>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy3: emdio2_phy@3 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 4 0x4>; /* Level high type */
-+		reg = <0x2>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy4: emdio2_phy@4 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 5 0x4>; /* Level high type */
-+		reg = <0x3>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+/* Update DPMAC connections to external PHYs, under the assumption of
-+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
-+ */
-+/* Leave Cortina nodes commented out until driver is integrated
-+ *&dpmac1 {
-+ *	phy-handle = <&mdio1_phy1>;
-+ *};
-+ *&dpmac2 {
-+ *	phy-handle = <&mdio1_phy2>;
-+ *};
-+ *&dpmac3 {
-+ *	phy-handle = <&mdio1_phy3>;
-+ *};
-+ *&dpmac4 {
-+ *	phy-handle = <&mdio1_phy4>;
-+ *};
-+ */
-+
-+&dpmac5 {
-+	phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac6 {
-+	phy-handle = <&mdio2_phy2>;
-+};
-+&dpmac7 {
-+	phy-handle = <&mdio2_phy3>;
-+};
-+&dpmac8 {
-+	phy-handle = <&mdio2_phy4>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
-@@ -118,6 +118,18 @@
- 	};
- };
- 
-+&timer {
-+	fsl,erratum-a008585;
-+};
-+
-+&usb0 {
-+	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+};
-+
-+&usb1 {
-+	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+};
-+
- &pcie1 {
- 	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
- 	       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
-@@ -22,3 +22,123 @@
- 		stdout-path = "serial0:115200n8";
- 	};
- };
-+
-+&ifc {
-+	boardctrl: board-control@3,0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
-+		reg = <3 0 0x300>;		/* TODO check address */
-+		ranges = <0 3 0 0x300>;
-+
-+		mdio_mux_emi1 {
-+			compatible = "mdio-mux-mmioreg", "mdio-mux";
-+			mdio-parent-bus = <&emdio1>;
-+			reg = <0x54 1>;		/* BRDCFG4 */
-+			mux-mask = <0xe0>;	/* EMI1_MDIO */
-+
-+			#address-cells=<1>;
-+			#size-cells = <0>;
-+
-+			/* Child MDIO buses, one for each riser card:
-+			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
-+			 * VSC8234 PHYs on the riser cards.
-+			 */
-+
-+			mdio_mux3: mdio@60 {
-+				reg = <0x60>;
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				mdio0_phy12: mdio_phy0@1c {
-+					reg = <0x1c>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy13: mdio_phy1@1d {
-+					reg = <0x1d>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy14: mdio_phy2@1e {
-+					reg = <0x1e>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy15: mdio_phy3@1f {
-+					reg = <0x1f>;
-+					phy-connection-type = "sgmii";
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&pcs_mdio1 {
-+		pcs_phy1: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x9C0 0x40>;/* lane H */
-+	};
-+};
-+
-+&pcs_mdio2 {
-+		pcs_phy2: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x980 0x40>;/* lane G */
-+	};
-+};
-+
-+&pcs_mdio3 {
-+		pcs_phy3: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x940 0x40>;/* lane F */
-+	};
-+};
-+
-+&pcs_mdio4 {
-+		pcs_phy4: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x900 0x40>;/* lane E */
-+	};
-+};
-+
-+/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
-+ * &dpmac1 {
-+ *	phy-handle = <&pcs_phy1>;
-+ * };
-+ *
-+ * &dpmac2 {
-+ *	phy-handle = <&pcs_phy2>;
-+ * };
-+ *
-+ * &dpmac3 {
-+ *	phy-handle = <&pcs_phy3>;
-+ * };
-+ *
-+ * &dpmac4 {
-+ *	phy-handle = <&pcs_phy4>;
-+ * };
-+ */
-+
-+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
-+&dpmac9 {
-+	phy-handle = <&mdio0_phy12>;
-+};
-+&dpmac10 {
-+	phy-handle = <&mdio0_phy13>;
-+};
-+&dpmac11 {
-+	phy-handle = <&mdio0_phy14>;
-+};
-+&dpmac12 {
-+	phy-handle = <&mdio0_phy15>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
-@@ -22,3 +22,83 @@
- 		stdout-path = "serial1:115200n8";
- 	};
- };
-+
-+&emdio1 {
-+	status = "disabled";
-+	/* CS4340 PHYs */
-+	mdio1_phy1: emdio1_phy@1 {
-+		reg = <0x10>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy2: emdio1_phy@2 {
-+		reg = <0x11>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy3: emdio1_phy@3 {
-+		reg = <0x12>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy4: emdio1_phy@4 {
-+		reg = <0x13>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+&emdio2 {
-+	/* AQR405 PHYs */
-+	mdio2_phy1: emdio2_phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 1 0x4>; /* Level high type */
-+		reg = <0x0>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy2: emdio2_phy@2 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 2 0x4>; /* Level high type */
-+		reg = <0x1>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy3: emdio2_phy@3 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 4 0x4>; /* Level high type */
-+		reg = <0x2>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy4: emdio2_phy@4 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 5 0x4>; /* Level high type */
-+		reg = <0x3>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+/* Update DPMAC connections to external PHYs, under the assumption of
-+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
-+ */
-+/* Leave Cortina PHYs commented out until proper driver is integrated
-+ *&dpmac1 {
-+ *	phy-handle = <&mdio1_phy1>;
-+ *};
-+ *&dpmac2 {
-+ *	phy-handle = <&mdio1_phy2>;
-+ *};
-+ *&dpmac3 {
-+ *	phy-handle = <&mdio1_phy3>;
-+ *};
-+ *&dpmac4 {
-+ *	phy-handle = <&mdio1_phy4>;
-+ *};
-+ */
-+
-+&dpmac5 {
-+	phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac6 {
-+	phy-handle = <&mdio2_phy2>;
-+};
-+&dpmac7 {
-+	phy-handle = <&mdio2_phy3>;
-+};
-+&dpmac8 {
-+	phy-handle = <&mdio2_phy4>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
-@@ -129,6 +129,7 @@
- 
- &qspi {
- 	status = "okay";
-+	fsl,qspi-has-second-chip;
- 	flash0: s25fl256s1@0 {
- 		#address-cells = <1>;
- 		#size-cells = <1>;
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
-@@ -49,6 +49,7 @@
- 		reg = <0x75>;
- 		#address-cells = <1>;
- 		#size-cells = <0>;
-+		i2c-mux-never-disable;
- 		i2c@1 {
- 			#address-cells = <1>;
- 			#size-cells = <0>;
-@@ -108,7 +109,15 @@
- };
- 
- &qspi {
--	status = "disabled";
-+	status = "okay";
-+	flash0: s25fs512s@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "spansion,m25p80";
-+		m25p,fast-read;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
- };
- 
- &sata0 {
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
-@@ -114,13 +114,12 @@
- 		};
- 	};
- 
--	timer {
-+	timer: timer {
- 		compatible = "arm,armv8-timer";
- 		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
- 			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
- 			     <1 11 4>, /* Virtual PPI, active-low */
- 			     <1 10 4>; /* Hypervisor PPI, active-low */
--		fsl,erratum-a008585;
- 	};
- 
- 	pmu {
-@@ -559,15 +558,126 @@
- 			#interrupt-cells = <2>;
- 		};
- 
-+		/* TODO: WRIOP (CCSR?) */
-+		emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
-+					  * E-MDIO1: 0x1_6000
-+					  */
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8B96000 0x0 0x1000>;
-+			device_type = "mdio";	/* TODO: is this necessary? */
-+			little-endian;	/* force the driver in LE mode */
-+
-+			/* Not necessary on the QDS, but needed on the RDB */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
-+					  * E-MDIO2: 0x1_7000
-+					  */
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8B97000 0x0 0x1000>;
-+			device_type = "mdio";	/* TODO: is this necessary? */
-+			little-endian;	/* force the driver in LE mode */
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio1: mdio@0x8c07000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c07000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio2: mdio@0x8c0b000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c0b000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio3: mdio@0x8c0f000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c0f000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio4: mdio@0x8c13000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c13000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio5: mdio@0x8c17000 {
-+			status = "disabled";
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c17000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio6: mdio@0x8c1b000 {
-+			status = "disabled";
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c1b000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio7: mdio@0x8c1f000 {
-+			status = "disabled";
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c1f000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio8: mdio@0x8c23000 {
-+			status = "disabled";
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c23000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
- 		i2c0: i2c@2000000 {
- 			status = "disabled";
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x2000000 0x0 0x10000>;
- 			interrupts = <0 34 0x4>; /* Level high type */
- 			clock-names = "i2c";
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 1>;
-+			scl-gpios = <&gpio3 10 0>;
- 		};
- 
- 		i2c1: i2c@2010000 {
-@@ -578,7 +688,7 @@
- 			reg = <0x0 0x2010000 0x0 0x10000>;
- 			interrupts = <0 34 0x4>; /* Level high type */
- 			clock-names = "i2c";
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 1>;
- 		};
- 
- 		i2c2: i2c@2020000 {
-@@ -589,7 +699,7 @@
- 			reg = <0x0 0x2020000 0x0 0x10000>;
- 			interrupts = <0 35 0x4>; /* Level high type */
- 			clock-names = "i2c";
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 1>;
- 		};
- 
- 		i2c3: i2c@2030000 {
-@@ -600,7 +710,7 @@
- 			reg = <0x0 0x2030000 0x0 0x10000>;
- 			interrupts = <0 35 0x4>; /* Level high type */
- 			clock-names = "i2c";
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 1>;
- 		};
- 
- 		ifc: ifc@2240000 {
-@@ -632,8 +742,8 @@
- 		pcie1: pcie@3400000 {
- 			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
- 			reg-names = "regs", "config";
--			interrupts = <0 108 0x4>; /* Level high type */
--			interrupt-names = "intr";
-+			interrupts = <0 108 0x4>; /* aer interrupt */
-+			interrupt-names = "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -641,6 +751,7 @@
- 			num-viewport = <6>;
- 			bus-range = <0x0 0xff>;
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 7>;
- 			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
-@@ -653,8 +764,8 @@
- 		pcie2: pcie@3500000 {
- 			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
- 			reg-names = "regs", "config";
--			interrupts = <0 113 0x4>; /* Level high type */
--			interrupt-names = "intr";
-+			interrupts = <0 113 0x4>; /* aer interrupt */
-+			interrupt-names = "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -662,6 +773,7 @@
- 			num-viewport = <6>;
- 			bus-range = <0x0 0xff>;
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 7>;
- 			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
-@@ -674,8 +786,8 @@
- 		pcie3: pcie@3600000 {
- 			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
- 			reg-names = "regs", "config";
--			interrupts = <0 118 0x4>; /* Level high type */
--			interrupt-names = "intr";
-+			interrupts = <0 118 0x4>; /* aer interrupt */
-+			interrupt-names = "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -683,6 +795,7 @@
- 			num-viewport = <256>;
- 			bus-range = <0x0 0xff>;
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 7>;
- 			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
-@@ -695,8 +808,8 @@
- 		pcie4: pcie@3700000 {
- 			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
- 			reg-names = "regs", "config";
--			interrupts = <0 123 0x4>; /* Level high type */
--			interrupt-names = "intr";
-+			interrupts = <0 123 0x4>; /* aer interrupt */
-+			interrupt-names = "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -704,6 +817,7 @@
- 			num-viewport = <6>;
- 			bus-range = <0x0 0xff>;
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 7>;
- 			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
-@@ -753,11 +867,22 @@
- 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
-+		serdes1: serdes@1ea0000 {
-+				reg = <0x0 0x1ea0000 0 0x00002000>;
-+				compatible = "fsl,serdes-10g";
-+		};
-+
- 		ccn@4000000 {
- 			compatible = "arm,ccn-504";
- 			reg = <0x0 0x04000000 0x0 0x01000000>;
- 			interrupts = <0 12 4>;
- 		};
-+
-+		ftm0: ftm0@2800000 {
-+			compatible = "fsl,ftm-alarm";
-+			reg = <0x0 0x2800000 0x0 0x10000>;
-+			interrupts = <0 44 4>;
-+		};
- 	};
- 
- 	ddr1: memory-controller@1080000 {