layerscape: add patches-5.4

Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

1 files changed, 574 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-5.4/302-dts-0007-arm64-dts-ls1043a-accumulated-change-for-ls1043a-boa.patch b/target/linux/layerscape/patches-5.4/302-dts-0007-arm64-dts-ls1043a-accumulated-change-for-ls1043a-boa.patch
new file mode 100644
index 0000000000..3455811c26
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/302-dts-0007-arm64-dts-ls1043a-accumulated-change-for-ls1043a-boa.patch
@@ -0,0 +1,574 @@
+From 794b9e55c77bf0ef34dfdb3b151a845c004b3ce3 Mon Sep 17 00:00:00 2001
+From: Li Yang <leoyang.li@nxp.com>
+Date: Thu, 2 May 2019 16:01:01 -0500
+Subject: [PATCH] arm64: dts: ls1043a: accumulated change for ls1043a boards
+
+commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce
+Author: Peng Ma <peng.ma@nxp.com>
+Date:   Wed Jul 25 08:53:07 2018 +0000
+
+    dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node
+support
+
+    add block-offset to support different virtual block offset for qdma
+    base on soc;
+    the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual
+    block,N based on block number of qdma;
+
+    Signed-off-by: Peng Ma <peng.ma@nxp.com>
+
+Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Date:   Mon Apr 2 16:22:40 2018 +0800
+
+    arm64: dts: ls1043a: add dts entry for A-010650
+
+    Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+
+commit a47e4bd0b5d076feb6d81601c16d5b79e53a92c8
+Author: Rajesh Bhagat <rajesh.bhagat@freescale.com>
+Date:   Wed Jan 27 11:37:25 2016 +0530
+
+    arm64: dts: ls1043a: Add configure-gfladj property to USB3 node
+
+    Add "configure-gfladj" boolean property to USB3 node. This property
+    is used to determine whether frame length adjustent is required
+    or not
+
+    Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+    Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
+
+commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
+Author: Changming Huang <jerry.huang@nxp.com>
+Date:   Wed Apr 19 12:49:50 2017 +0800
+
+    arm/arm64: dts: Add property snps incr burst type adjustment for
+INCR burst type for dwc3
+
+    Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
+    Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
+
+commit 8632d84e0fe187aa023a24f0dad0040c53e12450
+Author: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date:   Thu Jan 25 11:31:13 2018 +0530
+
+    arm64: dts: freescale: ls1043a: Modify DT nodes for qspi
+
+    Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+
+commit b1dc1ebed79e9aaab75fd06837d794ec2f1b624d
+Author: Ran Wang <ran.wang_1@nxp.com>
+Date:   Fri Jan 5 15:14:48 2018 +0800
+
+    arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node
+
+    Enable USB3 HW LPM feature for ls1043a and active patch for
+    snps erratum A-010131. It will disable U1/U2 temperary when
+    initiate U3 request.
+
+    Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
+
+commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d
+Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Date:   Tue Jun 13 13:14:26 2017 +0800
+
+    arm64: dts: correct the register range of dcfg
+
+    Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+
+commit f60e39fd51ad702e3a2613faaca40871a4763735
+Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Date:   Tue Aug 22 18:04:02 2017 +0800
+
+    arm64: dts: ls1043a: add pcf85263 rtc nodes
+
+    Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+
+commit 67c82e3c7b376139d7cee624589bedbc311f8868
+Author: jiaheng.fan <jiaheng.fan@nxp.com>
+Date:   Thu May 11 17:36:33 2017 +0800
+
+    arm64: dts: ls1021/ls1043/ls1046: add qdma nodes
+    Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
+
+commit c6d9c2498ee83669f9853100301edff9a5905caf
+Author: Wang Dongsheng <dongsheng.wang@nxp.com>
+Date:   Fri Apr 21 13:26:07 2017 +0800
+
+    arm64: dts: ls1043a: add ftm0 nodes
+
+    Add rcpm and ftm0 nodes. The Power Management related features
+    need these nodes.
+
+    Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+
+commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
+Author: Po Liu <po.liu@nxp.com>
+Date:   Fri Sep 30 17:11:36 2016 +0800
+
+    arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
+
+    Some platforms(NXP Layerscape for example) aer/pme interrupts was
+not
+    MSI/MSI-X/INTx but using interrupt line independently. This patch
+    add "aer", "pme" interrupt-names for aer/pme interrupt.
+
+    With the interrupt-names "aer", "pme" code could probe aer/pme
+interrupt
+    line for pcie root port, replace the aer/pme interrupt service irqs.
+
+    This is intend to fixup the Layerscape platforms which aer/pmes
+interrupts
+    was not MSI/MSI-X/INTx, but using interrupt line independently.
+
+    Since the interrupt-names "intr" never been used. Remove it.
+
+    Signed-off-by: Po Liu <po.liu@nxp.com>
+    Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+
+commit 4d20ecf029f1255520b30c103e1724c618b981c7
+Author: Zhao Qiang <qiang.zhao@nxp.com>
+Date:   Sun Jun 12 15:51:44 2016 +0800
+
+    arm64: dts: ls1043ardb: add ds26522 node
+
+    add ds26522 node to fsl-ls1043a-rdb.dts
+
+    Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+
+commit ca470562646ab058814fc4a1195016fb3266cdf5
+Author: Zhao Qiang <qiang.zhao@nxp.com>
+Date:   Sun Jun 12 15:44:11 2016 +0800
+
+    arm64: dts: ls1043ardb: add qe node
+
+    Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 162 ++++++++++++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts |  36 +++++
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi    | 108 +++++++++++++--
+ 3 files changed, 295 insertions(+), 11 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+@@ -24,6 +24,22 @@
+ 		serial1 = &duart1;
+ 		serial2 = &duart2;
+ 		serial3 = &duart3;
++		sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
++		sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
++		sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
++		sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
++		qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
++		qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
++		qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
++		qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
++		qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
++		qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
++		qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
++		qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
++		emi1_slot1 = &ls1043mdio_s1;
++		emi1_slot2 = &ls1043mdio_s2;
++		emi1_slot3 = &ls1043mdio_s3;
++		emi1_slot4 = &ls1043mdio_s4;
+ 	};
+ 
+ 	chosen {
+@@ -64,6 +80,8 @@
+ 	fpga: board-control@2,0 {
+ 		compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
+ 		reg = <0x2 0x0 0x0000100>;
++		#address-cells = <1>;
++		#size-cells = <1>;
+ 	};
+ };
+ 
+@@ -149,3 +167,147 @@
+ };
+ 
+ #include "fsl-ls1043-post.dtsi"
++
++&fman0 {
++	ethernet@e0000 {
++		phy-handle = <&qsgmii_phy_s2_p1>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@e2000 {
++		phy-handle = <&qsgmii_phy_s2_p2>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@e4000 {
++		phy-handle = <&rgmii_phy1>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e6000 {
++		phy-handle = <&rgmii_phy2>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e8000 {
++		phy-handle = <&qsgmii_phy_s2_p3>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@ea000 {
++		phy-handle = <&qsgmii_phy_s2_p4>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@f0000 { /* DTSEC9/10GEC1 */
++		fixed-link = <1 1 10000 0 0>;
++		phy-connection-type = "xgmii";
++	};
++};
++
++&fpga {
++	mdio-mux-emi1 {
++		compatible = "mdio-mux-mmioreg", "mdio-mux";
++		mdio-parent-bus = <&mdio0>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x54 1>;    /* BRDCFG4 */
++		mux-mask = <0xe0>; /* EMI1 */
++
++		/* On-board RGMII1 PHY */
++		ls1043mdio0: mdio@0 {
++			reg = <0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
++				reg = <0x1>;
++			};
++		};
++
++		/* On-board RGMII2 PHY */
++		ls1043mdio1: mdio@1 {
++			reg = <0x20>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
++				reg = <0x2>;
++			};
++		};
++
++		/* Slot 1 */
++		ls1043mdio_s1: mdio@2 {
++			reg = <0x40>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			qsgmii_phy_s1_p1: ethernet-phy@4 {
++				reg = <0x4>;
++			};
++			qsgmii_phy_s1_p2: ethernet-phy@5 {
++				reg = <0x5>;
++			};
++			qsgmii_phy_s1_p3: ethernet-phy@6 {
++				reg = <0x6>;
++			};
++			qsgmii_phy_s1_p4: ethernet-phy@7 {
++				reg = <0x7>;
++			};
++
++			sgmii_phy_s1_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++
++		/* Slot 2 */
++		ls1043mdio_s2: mdio@3 {
++			reg = <0x60>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			qsgmii_phy_s2_p1: ethernet-phy@8 {
++				reg = <0x8>;
++			};
++			qsgmii_phy_s2_p2: ethernet-phy@9 {
++				reg = <0x9>;
++			};
++			qsgmii_phy_s2_p3: ethernet-phy@a {
++				reg = <0xa>;
++			};
++			qsgmii_phy_s2_p4: ethernet-phy@b {
++				reg = <0xb>;
++			};
++
++			sgmii_phy_s2_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++
++		/* Slot 3 */
++		ls1043mdio_s3: mdio@4 {
++			reg = <0x80>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			sgmii_phy_s3_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++
++		/* Slot 4 */
++		ls1043mdio_s4: mdio@5 {
++			reg = <0xa0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			sgmii_phy_s4_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -49,6 +49,10 @@
+ 		compatible = "pericom,pt7c4338";
+ 		reg = <0x68>;
+ 	};
++	rtc@51 {
++		compatible = "nxp,pcf85263";
++		reg = <0x51>;
++	};
+ };
+ 
+ &ifc {
+@@ -94,6 +98,38 @@
+ 		reg = <0>;
+ 		spi-max-frequency = <1000000>; /* input clock */
+ 	};
++
++	slic@2 {
++		compatible = "maxim,ds26522";
++		reg = <2>;
++		spi-max-frequency = <2000000>;
++		fsl,spi-cs-sck-delay = <100>;
++		fsl,spi-sck-cs-delay = <50>;
++	};
++
++	slic@3 {
++		compatible = "maxim,ds26522";
++		reg = <3>;
++		spi-max-frequency = <2000000>;
++		fsl,spi-cs-sck-delay = <100>;
++		fsl,spi-sck-cs-delay = <50>;
++	};
++};
++
++&uqe {
++	ucc_hdlc: ucc@2000 {
++		compatible = "fsl,ucc-hdlc";
++		rx-clock-name = "clk8";
++		tx-clock-name = "clk9";
++		fsl,rx-sync-clock = "rsync_pin";
++		fsl,tx-sync-clock = "tsync_pin";
++		fsl,tx-timeslot-mask = <0xfffffffe>;
++		fsl,rx-timeslot-mask = <0xfffffffe>;
++		fsl,tdm-framer-type = "e1";
++		fsl,tdm-id = <0>;
++		fsl,siram-entry-id = <0>;
++		fsl,tdm-interface;
++	};
+ };
+ 
+ &duart0 {
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -277,7 +277,7 @@
+ 
+ 		dcfg: dcfg@1ee0000 {
+ 			compatible = "fsl,ls1043a-dcfg", "syscon";
+-			reg = <0x0 0x1ee0000 0x0 0x10000>;
++			reg = <0x0 0x1ee0000 0x0 0x1000>;
+ 			big-endian;
+ 		};
+ 
+@@ -411,7 +411,7 @@
+ 		};
+ 
+ 		i2c0: i2c@2180000 {
+-			compatible = "fsl,vf610-i2c";
++			compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			reg = <0x0 0x2180000 0x0 0x10000>;
+@@ -421,6 +421,7 @@
+ 			dmas = <&edma0 1 39>,
+ 			       <&edma0 1 38>;
+ 			dma-names = "tx", "rx";
++			scl-gpios = <&gpio4 12 0>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -525,6 +526,72 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 
++		uqe: uqe@2400000 {
++			#address-cells = <1>;
++			#size-cells = <1>;
++			device_type = "qe";
++			compatible = "fsl,qe", "simple-bus";
++			ranges = <0x0 0x0 0x2400000 0x40000>;
++			reg = <0x0 0x2400000 0x0 0x480>;
++			brg-frequency = <100000000>;
++			bus-frequency = <200000000>;
++
++			fsl,qe-num-riscs = <1>;
++			fsl,qe-num-snums = <28>;
++
++			qeic: qeic@80 {
++				compatible = "fsl,qe-ic";
++				reg = <0x80 0x80>;
++				#address-cells = <0>;
++				interrupt-controller;
++				#interrupt-cells = <1>;
++				interrupts = <0 77 0x04 0 77 0x04>;
++			};
++
++			si1: si@700 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,ls1043-qe-si",
++						"fsl,t1040-qe-si";
++				reg = <0x700 0x80>;
++			};
++
++			siram1: siram@1000 {
++				#address-cells = <1>;
++				#size-cells = <1>;
++				compatible = "fsl,ls1043-qe-siram",
++						"fsl,t1040-qe-siram";
++				reg = <0x1000 0x800>;
++			};
++
++			ucc@2000 {
++				cell-index = <1>;
++				reg = <0x2000 0x200>;
++				interrupts = <32>;
++				interrupt-parent = <&qeic>;
++			};
++
++			ucc@2200 {
++				cell-index = <3>;
++				reg = <0x2200 0x200>;
++				interrupts = <34>;
++				interrupt-parent = <&qeic>;
++			};
++
++			muram@10000 {
++				#address-cells = <1>;
++				#size-cells = <1>;
++				compatible = "fsl,qe-muram", "fsl,cpm-muram";
++				ranges = <0x0 0x10000 0x6000>;
++
++				data-only@0 {
++					compatible = "fsl,qe-muram-data",
++					"fsl,cpm-muram-data";
++					reg = <0x0 0x6000>;
++				};
++			};
++		};
++
+ 		lpuart0: serial@2950000 {
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x2950000 0x0 0x1000>;
+@@ -579,6 +646,16 @@
+ 			status = "disabled";
+ 		};
+ 
++		ftm0: ftm0@29d0000 {
++			compatible = "fsl,ftm-alarm";
++			reg = <0x0 0x29d0000 0x0 0x10000>,
++			      <0x0 0x1ee2140 0x0 0x4>;
++			reg-names = "ftm", "FlexTimer1";
++			interrupts = <0 86 0x4>;
++			big-endian;
++			status = "okay";
++		};
++
+ 		wdog0: wdog@2ad0000 {
+ 			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+ 			reg = <0x0 0x2ad0000 0x0 0x10000>;
+@@ -611,7 +688,10 @@
+ 			dr_mode = "host";
+ 			snps,quirk-frame-length-adjustment = <0x20>;
+ 			snps,dis_rxdet_inp3_quirk;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
+ 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++			configure-gfladj;
+ 		};
+ 
+ 		usb1: usb3@3000000 {
+@@ -621,7 +701,10 @@
+ 			dr_mode = "host";
+ 			snps,quirk-frame-length-adjustment = <0x20>;
+ 			snps,dis_rxdet_inp3_quirk;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
+ 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++			configure-gfladj;
+ 		};
+ 
+ 		usb2: usb3@3100000 {
+@@ -631,7 +714,10 @@
+ 			dr_mode = "host";
+ 			snps,quirk-frame-length-adjustment = <0x20>;
+ 			snps,dis_rxdet_inp3_quirk;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
+ 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++			configure-gfladj;
+ 		};
+ 
+ 		sata: sata@3200000 {
+@@ -670,9 +756,9 @@
+ 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+ 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names = "regs", "config";
+-			interrupts = <0 118 0x4>, /* controller interrupt */
+-				     <0 117 0x4>; /* PME interrupt */
+-			interrupt-names = "intr", "pme";
++			interrupts = <0 117 0x4>, /* PME interrupt */
++				     <0 118 0x4>; /* aer interrupt */
++			interrupt-names = "pme", "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
+@@ -696,9 +782,9 @@
+ 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+ 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names = "regs", "config";
+-			interrupts = <0 128 0x4>,
+-				     <0 127 0x4>;
+-			interrupt-names = "intr", "pme";
++			interrupts = <0 127 0x4>,
++				     <0 128 0x4>;
++			interrupt-names = "pme", "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
+@@ -722,9 +808,9 @@
+ 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+ 			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names = "regs", "config";
+-			interrupts = <0 162 0x4>,
+-				     <0 161 0x4>;
+-			interrupt-names = "intr", "pme";
++			interrupts = <0 161 0x4>,
++				     <0 162 0x4>;
++			interrupt-names = "pme", "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";