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author | Yangbo Lu <yangbo.lu@nxp.com> | 2020-04-10 10:47:05 +0800 |
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committer | Petr Štetiar <ynezz@true.cz> | 2020-05-07 12:53:06 +0200 |
commit | cddd4591404fb4c53dc0b3c0b15b942cdbed4356 (patch) | |
tree | 392c1179de46b0f804e3789edca19069b64e6b44 /target/linux/layerscape/patches-5.4/301-arch-0005-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch | |
parent | d1d2c0b5579ea4f69a42246c9318539d61ba1999 (diff) | |
download | upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.tar.gz upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.tar.bz2 upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.zip |
layerscape: add patches-5.4
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/
For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.
The patches are sorted into the following categories:
301-arch-xxxx
302-dts-xxxx
303-core-xxxx
701-net-xxxx
801-audio-xxxx
802-can-xxxx
803-clock-xxxx
804-crypto-xxxx
805-display-xxxx
806-dma-xxxx
807-gpio-xxxx
808-i2c-xxxx
809-jailhouse-xxxx
810-keys-xxxx
811-kvm-xxxx
812-pcie-xxxx
813-pm-xxxx
814-qe-xxxx
815-sata-xxxx
816-sdhc-xxxx
817-spi-xxxx
818-thermal-xxxx
819-uart-xxxx
820-usb-xxxx
821-vfio-xxxx
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-5.4/301-arch-0005-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch')
-rw-r--r-- | target/linux/layerscape/patches-5.4/301-arch-0005-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/301-arch-0005-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch b/target/linux/layerscape/patches-5.4/301-arch-0005-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch new file mode 100644 index 0000000000..ddb77d438b --- /dev/null +++ b/target/linux/layerscape/patches-5.4/301-arch-0005-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch @@ -0,0 +1,79 @@ +From 3bc37b0ee99b9d66ac47aea02784242cb3224366 Mon Sep 17 00:00:00 2001 +From: Zhao Qiang <B45475@freescale.com> +Date: Fri, 10 Oct 2014 10:38:48 +0800 +Subject: [PATCH] arch: arm: add ARM specific fucntions required for ehci fsl + driver + +Add below functions for ARM platform which are used by ehci fsl driver: +1. spin_event_timeout function +2. set/clear bits functions + +Signed-off-by: Zhao Qiang <B45475@freescale.com> +Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> +--- + arch/arm/include/asm/delay.h | 16 ++++++++++++++++ + arch/arm/include/asm/io.h | 28 ++++++++++++++++++++++++++++ + 2 files changed, 44 insertions(+) + +--- a/arch/arm/include/asm/delay.h ++++ b/arch/arm/include/asm/delay.h +@@ -85,6 +85,22 @@ extern void __bad_udelay(void); + __const_udelay((n) * UDELAY_MULT)) : \ + __udelay(n)) + ++#define spin_event_timeout(condition, timeout, delay) \ ++({ \ ++ typeof(condition) __ret; \ ++ int i = 0; \ ++ while (!(__ret = (condition)) && (i++ < timeout)) { \ ++ if (delay) \ ++ udelay(delay); \ ++ else \ ++ cpu_relax(); \ ++ udelay(1); \ ++ } \ ++ if (!__ret) \ ++ __ret = (condition); \ ++ __ret; \ ++}) ++ + /* Loop-based definitions for assembly code. */ + extern void __loop_delay(unsigned long loops); + extern void __loop_udelay(unsigned long usecs); +--- a/arch/arm/include/asm/io.h ++++ b/arch/arm/include/asm/io.h +@@ -224,6 +224,34 @@ void __iomem *pci_remap_cfgspace(resourc + #endif + #endif + ++/* access ports */ ++#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) ++#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) ++ ++#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) ++#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) ++ ++#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) ++#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) ++ ++/* Clear and set bits in one shot. These macros can be used to clear and ++ * set multiple bits in a register using a single read-modify-write. These ++ * macros can also be used to set a multiple-bit bit pattern using a mask, ++ * by specifying the mask in the 'clear' parameter and the new bit pattern ++ * in the 'set' parameter. ++ */ ++ ++#define clrsetbits_be32(addr, clear, set) \ ++ iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) ++#define clrsetbits_le32(addr, clear, set) \ ++ iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr)) ++#define clrsetbits_be16(addr, clear, set) \ ++ iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) ++#define clrsetbits_le16(addr, clear, set) \ ++ iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr)) ++#define clrsetbits_8(addr, clear, set) \ ++ iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) ++ + /* + * IO port access primitives + * ------------------------- |