layerscape: update kernel patches

Updated kernel patches to align layerscape kernel
with latest LSDK linux (LSDK-17.09-update-103017-V4.9 tag).

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

1 files changed, 66 insertions, 97 deletions

diff --git a/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch b/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
index 445a6fa028..6dbd984f2f 100644
--- a/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
@@ -1,4 +1,4 @@
-From 120fa458ffe2250ea58578ccfc85e674005463dc Mon Sep 17 00:00:00 2001
+From a3757157751a8a5302ee5e11faf828dc5db02018 Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
 Date: Mon, 25 Sep 2017 10:53:50 +0800
 Subject: [PATCH] mtd: spi-nor: support layerscape
@@ -18,14 +18,16 @@ Signed-off-by: Ash Benz <ash.benz@bk.ru>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
  drivers/mtd/mtdchar.c             |   2 +-
- drivers/mtd/spi-nor/fsl-quadspi.c | 356 +++++++++++++++++++++++++++++++-------
- drivers/mtd/spi-nor/spi-nor.c     | 136 +++++++++++++--
+ drivers/mtd/spi-nor/fsl-quadspi.c | 327 +++++++++++++++++++++++++++++++-------
+ drivers/mtd/spi-nor/spi-nor.c     | 136 ++++++++++++++--
  include/linux/mtd/spi-nor.h       |  14 +-
- 4 files changed, 432 insertions(+), 76 deletions(-)
+ 4 files changed, 409 insertions(+), 70 deletions(-)
 
+diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c
+index 2a47a3f0..4f21401d 100644
 --- a/drivers/mtd/mtdchar.c
 +++ b/drivers/mtd/mtdchar.c
-@@ -451,7 +451,7 @@ static int mtdchar_readoob(struct file *
+@@ -451,7 +451,7 @@ static int mtdchar_readoob(struct file *file, struct mtd_info *mtd,
  	 * data. For our userspace tools it is important to dump areas
  	 * with ECC errors!
  	 * For kernel internal usage it also might return -EUCLEAN
@@ -34,6 +36,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	 * been corrected by the ECC algorithm.
  	 *
  	 * Note: currently the standard NAND function, nand_read_oob_std,
+diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
+index 5c82e4ef..33ecc27a 100644
 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
 @@ -41,6 +41,8 @@
@@ -86,7 +90,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	.devtype = FSL_QUADSPI_VYBRID,
  	.rxfifo = 128,
  	.txfifo = 64,
-@@ -232,7 +241,7 @@ static struct fsl_qspi_devtype_data vybr
+@@ -232,7 +241,7 @@ static struct fsl_qspi_devtype_data vybrid_data = {
  	.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
  };
  
@@ -95,7 +99,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	.devtype = FSL_QUADSPI_IMX6SX,
  	.rxfifo = 128,
  	.txfifo = 512,
-@@ -241,7 +250,7 @@ static struct fsl_qspi_devtype_data imx6
+@@ -241,7 +250,7 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
  		       | QUADSPI_QUIRK_TKT245618,
  };
  
@@ -104,7 +108,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	.devtype = FSL_QUADSPI_IMX7D,
  	.rxfifo = 512,
  	.txfifo = 512,
-@@ -250,7 +259,7 @@ static struct fsl_qspi_devtype_data imx7
+@@ -250,7 +259,7 @@ static struct fsl_qspi_devtype_data imx7d_data = {
  		       | QUADSPI_QUIRK_4X_INT_CLK,
  };
  
@@ -113,7 +117,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	.devtype = FSL_QUADSPI_IMX6UL,
  	.rxfifo = 128,
  	.txfifo = 512,
-@@ -267,6 +276,14 @@ static struct fsl_qspi_devtype_data ls10
+@@ -267,6 +276,14 @@ static struct fsl_qspi_devtype_data ls1021a_data = {
  	.driver_data = 0,
  };
  
@@ -136,7 +140,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	unsigned int chip_base_addr; /* We may support two chips. */
  	bool has_second_chip;
  	bool big_endian;
-@@ -309,6 +327,23 @@ static inline int needs_wakeup_wait_mode
+@@ -309,6 +327,23 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
  	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
  }
  
@@ -160,7 +164,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  /*
   * R/W functions for big- or little-endian registers:
   * The qSPI controller's endian is independent of the CPU core's endian.
-@@ -331,6 +366,31 @@ static u32 qspi_readl(struct fsl_qspi *q
+@@ -331,6 +366,31 @@ static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
  		return ioread32(addr);
  }
  
@@ -192,7 +196,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  /*
   * An IC bug makes us to re-arrange the 32-bit data.
   * The following chips, such as IMX6SLX, have fixed this bug.
-@@ -373,8 +433,15 @@ static void fsl_qspi_init_lut(struct fsl
+@@ -373,8 +433,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
  	void __iomem *base = q->iobase;
  	int rxfifo = q->devtype_data->rxfifo;
  	u32 lut_base;
@@ -209,7 +213,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	fsl_qspi_unlock_lut(q);
  
-@@ -382,25 +449,51 @@ static void fsl_qspi_init_lut(struct fsl
+@@ -382,25 +449,51 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
  	for (i = 0; i < QUADSPI_LUT_NUM; i++)
  		qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
  
@@ -226,10 +230,11 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 -		addrlen = ADDR32BIT;
 -		dummy = 8;
 -	}
+-
+-	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
 +	/* Read */
 +	lut_base = SEQID_READ * 4;
- 
--	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++
 +	if (nor->flash_read == SPI_NOR_FAST) {
 +		qspi_writel(q, LUT0(CMD, PAD1, read_op) |
 +			    LUT1(ADDR, PAD1, addrlen),
@@ -276,7 +281,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	/* Write enable */
  	lut_base = SEQID_WREN * 4;
  	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
-@@ -409,16 +502,8 @@ static void fsl_qspi_init_lut(struct fsl
+@@ -409,16 +502,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
  	/* Page Program */
  	lut_base = SEQID_PP * 4;
  
@@ -295,7 +300,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  			base + QUADSPI_LUT(lut_base));
  	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
  			base + QUADSPI_LUT(lut_base + 1));
-@@ -432,10 +517,8 @@ static void fsl_qspi_init_lut(struct fsl
+@@ -432,10 +517,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
  	/* Erase a sector */
  	lut_base = SEQID_SE * 4;
  
@@ -308,7 +313,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  			base + QUADSPI_LUT(lut_base));
  
  	/* Erase the whole chip */
-@@ -476,6 +559,44 @@ static void fsl_qspi_init_lut(struct fsl
+@@ -476,6 +559,44 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
  	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
  			base + QUADSPI_LUT(lut_base));
  
@@ -353,7 +358,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	fsl_qspi_lock_lut(q);
  }
  
-@@ -483,8 +604,24 @@ static void fsl_qspi_init_lut(struct fsl
+@@ -483,8 +604,24 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
  static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
  {
  	switch (cmd) {
@@ -379,7 +384,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	case SPINOR_OP_WREN:
  		return SEQID_WREN;
  	case SPINOR_OP_WRDI:
-@@ -496,6 +633,7 @@ static int fsl_qspi_get_seqid(struct fsl
+@@ -496,6 +633,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
  	case SPINOR_OP_CHIP_ERASE:
  		return SEQID_CHIP_ERASE;
  	case SPINOR_OP_PP:
@@ -387,7 +392,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		return SEQID_PP;
  	case SPINOR_OP_RDID:
  		return SEQID_RDID;
-@@ -507,6 +645,8 @@ static int fsl_qspi_get_seqid(struct fsl
+@@ -507,6 +645,8 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
  		return SEQID_EN4B;
  	case SPINOR_OP_BRWR:
  		return SEQID_BRWR;
@@ -396,7 +401,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	default:
  		if (cmd == q->nor[0].erase_opcode)
  			return SEQID_SE;
-@@ -531,8 +671,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
+@@ -531,8 +671,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
  	/* save the reg */
  	reg = qspi_readl(q, base + QUADSPI_MCR);
  
@@ -410,7 +415,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
  			base + QUADSPI_RBCT);
  	qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
-@@ -582,10 +725,10 @@ static void fsl_qspi_read_data(struct fs
+@@ -582,10 +725,10 @@ static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
  				q->chip_base_addr, tmp);
  
  		if (len >= 4) {
@@ -423,7 +428,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  			break;
  		}
  
-@@ -619,11 +762,12 @@ static inline void fsl_qspi_invalid(stru
+@@ -619,11 +762,12 @@ static inline void fsl_qspi_invalid(struct fsl_qspi *q)
  }
  
  static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
@@ -437,7 +442,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
  		q->chip_base_addr, to, count);
-@@ -633,10 +777,13 @@ static ssize_t fsl_qspi_nor_write(struct
+@@ -633,10 +777,13 @@ static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
  	qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
  
  	/* fill the TX data to the FIFO */
@@ -453,7 +458,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	}
  
  	/* fill the TXFIFO upto 16 bytes for i.MX7d */
-@@ -657,11 +804,43 @@ static void fsl_qspi_set_map_addr(struct
+@@ -657,11 +804,43 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
  {
  	int nor_size = q->nor_size;
  	void __iomem *base = q->iobase;
@@ -501,50 +506,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  }
  
  /*
-@@ -681,19 +860,36 @@ static void fsl_qspi_init_abh_read(struc
- {
- 	void __iomem *base = q->iobase;
- 	int seqid;
-+	const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
- 
- 	/* AHB configuration for access buffer 0/1/2 .*/
- 	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
- 	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
- 	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
-+
- 	/*
--	 * Set ADATSZ with the maximum AHB buffer size to improve the
--	 * read performance.
-+	 * Errata: A-009282: QuadSPI data prefetch may result in incorrect data
-+	 * Workaround: Keep the read data size to 64 bits (8 bytes).
-+	 * This disables the prefetch on the AHB buffer and
-+	 * prevents this issue from occurring.
- 	 */
--	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
--			((q->devtype_data->ahb_buf_size / 8)
--			<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
--			base + QUADSPI_BUF3CR);
-+	if (devtype_data->devtype == FSL_QUADSPI_LS2080A ||
-+	    devtype_data->devtype == FSL_QUADSPI_LS1021A) {
-+
-+		qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
-+				(1 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
-+				base + QUADSPI_BUF3CR);
-+
-+	} else {
-+		/*
-+		 * Set ADATSZ with the maximum AHB buffer size to improve the
-+		 * read performance.
-+		*/
-+		qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
-+				((q->devtype_data->ahb_buf_size / 8)
-+				<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
-+				base + QUADSPI_BUF3CR);
-+	}
- 
- 	/* We only use the buffer3 */
- 	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
-@@ -704,6 +900,11 @@ static void fsl_qspi_init_abh_read(struc
+@@ -704,6 +883,11 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
  	seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
  	qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
  		q->iobase + QUADSPI_BFGENCR);
@@ -556,7 +518,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  }
  
  /* This function was used to prepare and enable QSPI clock */
-@@ -822,6 +1023,7 @@ static const struct of_device_id fsl_qsp
+@@ -822,6 +1006,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
  	{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
  	{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
  	{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
@@ -564,21 +526,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	{ /* sentinel */ }
  };
  MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-@@ -835,8 +1037,12 @@ static int fsl_qspi_read_reg(struct spi_
+@@ -835,8 +1020,12 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  {
  	int ret;
  	struct fsl_qspi *q = nor->priv;
 +	u32 to = 0;
-+
-+	if (opcode == SPINOR_OP_SPANSION_RDAR)
-+		u8tou32(&to, nor->cmd_buf, 4);
  
 -	ret = fsl_qspi_runcmd(q, opcode, 0, len);
++	if (opcode == SPINOR_OP_SPANSION_RDAR)
++		u8tou32(&to, nor->cmd_buf, 4);
++
 +	ret = fsl_qspi_runcmd(q, opcode, to, len);
  	if (ret)
  		return ret;
  
-@@ -848,9 +1054,13 @@ static int fsl_qspi_write_reg(struct spi
+@@ -848,9 +1037,13 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  {
  	struct fsl_qspi *q = nor->priv;
  	int ret;
@@ -593,7 +555,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		if (ret)
  			return ret;
  
-@@ -859,7 +1069,7 @@ static int fsl_qspi_write_reg(struct spi
+@@ -859,7 +1052,7 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  
  	} else if (len > 0) {
  		ret = fsl_qspi_nor_write(q, nor, opcode, 0,
@@ -602,7 +564,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		if (ret > 0)
  			return 0;
  	} else {
-@@ -875,7 +1085,7 @@ static ssize_t fsl_qspi_write(struct spi
+@@ -875,7 +1068,7 @@ static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
  {
  	struct fsl_qspi *q = nor->priv;
  	ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
@@ -611,7 +573,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	/* invalid the data in the AHB buffer. */
  	fsl_qspi_invalid(q);
-@@ -922,7 +1132,7 @@ static ssize_t fsl_qspi_read(struct spi_
+@@ -922,7 +1115,7 @@ static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
  		len);
  
  	/* Read out the data directly from the AHB buffer.*/
@@ -620,7 +582,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		len);
  
  	return len;
-@@ -980,6 +1190,8 @@ static int fsl_qspi_probe(struct platfor
+@@ -980,6 +1173,8 @@ static int fsl_qspi_probe(struct platform_device *pdev)
  	struct spi_nor *nor;
  	struct mtd_info *mtd;
  	int ret, i = 0;
@@ -629,7 +591,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
  	if (!q)
-@@ -1027,6 +1239,12 @@ static int fsl_qspi_probe(struct platfor
+@@ -1027,6 +1222,12 @@ static int fsl_qspi_probe(struct platform_device *pdev)
  		goto clk_failed;
  	}
  
@@ -642,7 +604,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	/* find the irq */
  	ret = platform_get_irq(pdev, 0);
  	if (ret < 0) {
-@@ -1050,6 +1268,7 @@ static int fsl_qspi_probe(struct platfor
+@@ -1050,6 +1251,7 @@ static int fsl_qspi_probe(struct platform_device *pdev)
  
  	mutex_init(&q->lock);
  
@@ -650,7 +612,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	/* iterate the subnodes. */
  	for_each_available_child_of_node(dev->of_node, np) {
  		/* skip the holes */
-@@ -1076,18 +1295,25 @@ static int fsl_qspi_probe(struct platfor
+@@ -1076,18 +1278,25 @@ static int fsl_qspi_probe(struct platform_device *pdev)
  		ret = of_property_read_u32(np, "spi-max-frequency",
  				&q->clk_rate);
  		if (ret < 0)
@@ -680,7 +642,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  		/* Set the correct NOR size now. */
  		if (q->nor_size == 0) {
-@@ -1110,8 +1336,12 @@ static int fsl_qspi_probe(struct platfor
+@@ -1110,8 +1319,12 @@ static int fsl_qspi_probe(struct platform_device *pdev)
  			nor->page_size = q->devtype_data->txfifo;
  
  		i++;
@@ -693,6 +655,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	/* finish the rest init. */
  	ret = fsl_qspi_nor_setup_last(q);
  	if (ret)
+diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
+index 793d321d..190e0e45 100644
 --- a/drivers/mtd/spi-nor/spi-nor.c
 +++ b/drivers/mtd/spi-nor/spi-nor.c
 @@ -40,6 +40,13 @@
@@ -740,7 +704,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
   */
  static int read_cr(struct spi_nor *nor)
  {
-@@ -160,6 +170,8 @@ static inline int spi_nor_read_dummy_cyc
+@@ -160,6 +170,8 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
  	case SPI_NOR_DUAL:
  	case SPI_NOR_QUAD:
  		return 8;
@@ -749,7 +713,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	case SPI_NOR_NORMAL:
  		return 0;
  	}
-@@ -961,6 +973,8 @@ static const struct flash_info spi_nor_i
+@@ -961,6 +973,8 @@ static const struct flash_info spi_nor_ids[] = {
  
  	/* ESMT */
  	{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
@@ -758,7 +722,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	/* Everspin */
  	{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
-@@ -1014,12 +1028,15 @@ static const struct flash_info spi_nor_i
+@@ -1014,12 +1028,15 @@ static const struct flash_info spi_nor_ids[] = {
  	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, SECT_4K) },
  	{ "mx25l3255e",  INFO(0xc29e16, 0, 64 * 1024,  64, SECT_4K) },
  	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
@@ -775,7 +739,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
  	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
  	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
-@@ -1033,10 +1050,11 @@ static const struct flash_info spi_nor_i
+@@ -1033,10 +1050,11 @@ static const struct flash_info spi_nor_ids[] = {
  	{ "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
  	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
  	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
@@ -789,7 +753,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	/* PMC */
  	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
-@@ -1054,8 +1072,11 @@ static const struct flash_info spi_nor_i
+@@ -1054,8 +1072,11 @@ static const struct flash_info spi_nor_ids[] = {
  	{ "s70fl01gs",  INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
  	{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },
  	{ "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },
@@ -802,7 +766,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	{ "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  	{ "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },
  	{ "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },
-@@ -1130,6 +1151,9 @@ static const struct flash_info spi_nor_i
+@@ -1130,6 +1151,9 @@ static const struct flash_info spi_nor_ids[] = {
  	{ "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
  	{ "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
  	{ "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
@@ -812,7 +776,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	{ "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
  	{
  		"w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
-@@ -1192,6 +1216,53 @@ static const struct flash_info *spi_nor_
+@@ -1192,6 +1216,53 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  		id[0], id[1], id[2]);
  	return ERR_PTR(-ENODEV);
  }
@@ -866,7 +830,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
  			size_t *retlen, u_char *buf)
-@@ -1411,7 +1482,7 @@ static int macronix_quad_enable(struct s
+@@ -1411,7 +1482,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
   * Write status Register and configuration register with 2 bytes
   * The first byte will be written to the status register, while the
   * second byte will be written to the configuration register.
@@ -875,7 +839,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
   */
  static int write_sr_cr(struct spi_nor *nor, u16 val)
  {
-@@ -1459,6 +1530,24 @@ static int spansion_quad_enable(struct s
+@@ -1459,6 +1530,24 @@ static int spansion_quad_enable(struct spi_nor *nor)
  	return 0;
  }
  
@@ -900,7 +864,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
  {
  	int status;
-@@ -1604,9 +1693,25 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1604,9 +1693,25 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
  		write_sr(nor, 0);
  		spi_nor_wait_till_ready(nor);
  	}
@@ -926,7 +890,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	mtd->priv = nor;
  	mtd->type = MTD_NORFLASH;
  	mtd->writesize = 1;
-@@ -1639,6 +1744,8 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1639,6 +1744,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
  		nor->flags |= SNOR_F_USE_FSR;
  	if (info->flags & SPI_NOR_HAS_TB)
  		nor->flags |= SNOR_F_HAS_SR_TB;
@@ -935,7 +899,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
  	/* prefer "small sector" erase if possible */
-@@ -1676,9 +1783,15 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1676,9 +1783,15 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
  	/* Some devices cannot do fast-read, no matter what DT tells us */
  	if (info->flags & SPI_NOR_NO_FR)
  		nor->flash_read = SPI_NOR_NORMAL;
@@ -954,7 +918,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		ret = set_quad_mode(nor, info);
  		if (ret) {
  			dev_err(dev, "quad mode not supported\n");
-@@ -1691,6 +1804,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1691,6 +1804,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
  
  	/* Default commands */
  	switch (nor->flash_read) {
@@ -964,6 +928,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	case SPI_NOR_QUAD:
  		nor->read_opcode = SPINOR_OP_READ_1_1_4;
  		break;
+diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
+index f2a71803..5003ff64 100644
 --- a/include/linux/mtd/spi-nor.h
 +++ b/include/linux/mtd/spi-nor.h
 @@ -31,10 +31,10 @@
@@ -1028,3 +994,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+-- 
+2.14.1
+