layerscape: add ls2088ardb device support

The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.

Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 103 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch b/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch
new file mode 100644
index 0000000000..08e1ecba9a
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch
@@ -0,0 +1,103 @@
+From 562f1311b529d81662ed41786b8d240db2e2ff51 Mon Sep 17 00:00:00 2001
+From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
+Date: Tue, 6 Dec 2016 15:30:39 +0800
+Subject: [PATCH 237/238] pcie/ls208x: use unified compatible
+ "fsl,ls2080a-pcie" for ls208x
+
+To avoid unnecessary reduplication, let's use unified compatible
+"fsl,ls2080a-pcie" for ls2080a, ls2085a, ls2088a.
+
+This patch fixes issue of pcie not working on ls2088a.
+
+Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi |   12 ++++--------
+ drivers/pci/host/pci-layerscape.c              |   13 ++++++++-----
+ 2 files changed, 12 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+index bd69942..07c917b 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+@@ -513,8 +513,7 @@
+ 	};
+ 
+ 	pcie1: pcie@3400000 {
+-		compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
+-			     "fsl,ls2085a-pcie", "snps,dw-pcie";
++		compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
+ 		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+ 		       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+ 		reg-names = "regs", "config";
+@@ -539,8 +538,7 @@
+ 	};
+ 
+ 	pcie2: pcie@3500000 {
+-		compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
+-			     "fsl,ls2085a-pcie", "snps,dw-pcie";
++		compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
+ 		reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+ 		       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+ 		reg-names = "regs", "config";
+@@ -565,8 +563,7 @@
+ 	};
+ 
+ 	pcie3: pcie@3600000 {
+-		compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
+-			     "fsl,ls2085a-pcie", "snps,dw-pcie";
++		compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
+ 		reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+ 		       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+ 		reg-names = "regs", "config";
+@@ -591,8 +588,7 @@
+ 	};
+ 
+ 	pcie4: pcie@3700000 {
+-		compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
+-			     "fsl,ls2085a-pcie", "snps,dw-pcie";
++		compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
+ 		reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
+ 		       0x38 0x00000000 0x0 0x00002000>; /* configuration space */
+ 		reg-names = "regs", "config";
+diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
+index 00feabf..3e2100d 100644
+--- a/drivers/pci/host/pci-layerscape.c
++++ b/drivers/pci/host/pci-layerscape.c
+@@ -158,9 +158,14 @@ static void ls1021_pcie_host_init(struct pcie_port *pp)
+ static int ls_pcie_link_up(struct pcie_port *pp)
+ {
+ 	struct ls_pcie *pcie = to_ls_pcie(pp);
+-	u32 state;
++	u32 state, offset;
++
++        if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL))
++                offset = 0x407fc;
++        else
++                offset = pcie->drvdata->lut_dbg;
+ 
+-	state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
++	state = (ioread32(pcie->lut + offset) >>
+ 		 pcie->drvdata->ltssm_shift) &
+ 		 LTSSM_STATE_MASK;
+ 
+@@ -261,7 +266,6 @@ static const struct of_device_id ls_pcie_of_match[] = {
+ 	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
+ 	{ .compatible = "fsl,ls1088a-pcie", .data = &ls1088_drvdata },
+ 	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
+-	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
+@@ -315,8 +319,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
+ 	if (!ls_pcie_is_bridge(pcie))
+ 		return -ENODEV;
+ 
+-	if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2085a-pcie") ||
+-	of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") ||
++	if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") ||
+ 	of_device_is_compatible(pdev->dev.of_node, "fsl,ls1088a-pcie")) {
+ 		int len;
+ 		const u32 *prop;
+-- 
+1.7.9.5
+