layerscape: add 64b/32b target for ls1043ardb device

Add support for NXP layerscape ls1043ardb 64b/32b Dev board.

LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores.
ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC,
I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc.

64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from
NXP QorIQ SDK release.

All of 4.4 kernel patches porting from SDK release or upstream.

QorIQ SDK ISOs can be downloaded from this location:
http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 59 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.4/7024-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch b/target/linux/layerscape/patches-4.4/7024-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch
new file mode 100644
index 0000000000..f0247f0dea
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/7024-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch
@@ -0,0 +1,59 @@
+From 2dcd28f7b4f5b92686da45f4ec46802026fb8573 Mon Sep 17 00:00:00 2001
+From: Roy Pledge <Roy.Pledge@freescale.com>
+Date: Mon, 11 Jul 2016 14:34:59 +0800
+Subject: [PATCH 24/70] Add APIs to setup HugeTLB mappings for USDPAA
+
+commit 189653d40d5dc41b8bd4cfb61f766bd8a89b1e34
+[context adjustment]
+
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/powerpc/mm/fsl_booke_mmu.c |   14 +++++++++++++-
+ arch/powerpc/mm/mmu_decl.h      |    6 ++++++
+ 2 files changed, 19 insertions(+), 1 deletion(-)
+
+--- a/arch/powerpc/mm/fsl_booke_mmu.c
++++ b/arch/powerpc/mm/fsl_booke_mmu.c
+@@ -105,7 +105,7 @@ unsigned long p_mapped_by_tlbcam(phys_ad
+  * an unsigned long (for example, 32-bit implementations cannot support a 4GB
+  * size).
+  */
+-static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
++void settlbcam(int index, unsigned long virt, phys_addr_t phys,
+ 		unsigned long size, unsigned long flags, unsigned int pid)
+ {
+ 	unsigned int tsize;
+@@ -143,6 +143,18 @@ static void settlbcam(int index, unsigne
+ 	tlbcam_addrs[index].phys = phys;
+ }
+ 
++void cleartlbcam(unsigned long virt, unsigned int pid)
++{
++        int i = 0;
++        for (i = 0; i < NUM_TLBCAMS; i++) {
++                if (tlbcam_addrs[i].start == virt) {
++                        TLBCAM[i].MAS1 = 0;
++                        loadcam_entry(i);
++                        return;
++                }
++        }
++}
++
+ unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
+ 			  phys_addr_t phys)
+ {
+--- a/arch/powerpc/mm/mmu_decl.h
++++ b/arch/powerpc/mm/mmu_decl.h
+@@ -91,6 +91,12 @@ extern void _tlbia(void);
+ 
+ #endif /* CONFIG_PPC_MMU_NOHASH */
+ 
++void settlbcam(int index, unsigned long virt, phys_addr_t phys,
++               unsigned long size, unsigned long flags, unsigned int pid);
++
++void cleartlbcam(unsigned long virt, unsigned int pid);
++
++
+ #ifdef CONFIG_PPC32
+ 
+ extern void mapin_ram(void);