diff options
| author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:14:32 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
| commit | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (patch) | |
| tree | d92c7296f82d46d1b2da30933a97595f6cb8ad66 /target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch | |
| parent | a34f96d6cf80c7c3c425076714d9c4caa67e3670 (diff) | |
| download | upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.tar.gz upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.tar.bz2 upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.zip | |
layerscape: add 64b/32b target for ls1043ardb device
Add support for NXP layerscape ls1043ardb 64b/32b Dev board.
LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores.
ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC,
I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc.
64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from
NXP QorIQ SDK release.
All of 4.4 kernel patches porting from SDK release or upstream.
QorIQ SDK ISOs can be downloaded from this location:
http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch b/target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch new file mode 100644 index 0000000000..0eac882c3e --- /dev/null +++ b/target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch @@ -0,0 +1,79 @@ +From 03eea243622d85d59653ee076ce43ac0653dc51d Mon Sep 17 00:00:00 2001 +From: Zhao Qiang <B45475@freescale.com> +Date: Fri, 10 Oct 2014 10:38:48 +0800 +Subject: [PATCH 39/70] arch: arm: add ARM specific fucntions required for + ehci fsl driver + +Add below functions for ARM platform which are used by ehci fsl driver: +1. spin_event_timeout function +2. set/clear bits functions + +Signed-off-by: Zhao Qiang <B45475@freescale.com> +Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> +--- + arch/arm/include/asm/delay.h | 16 ++++++++++++++++ + arch/arm/include/asm/io.h | 28 ++++++++++++++++++++++++++++ + 2 files changed, 44 insertions(+) + +--- a/arch/arm/include/asm/delay.h ++++ b/arch/arm/include/asm/delay.h +@@ -57,6 +57,22 @@ extern void __bad_udelay(void); + __const_udelay((n) * UDELAY_MULT)) : \ + __udelay(n)) + ++#define spin_event_timeout(condition, timeout, delay) \ ++({ \ ++ typeof(condition) __ret; \ ++ int i = 0; \ ++ while (!(__ret = (condition)) && (i++ < timeout)) { \ ++ if (delay) \ ++ udelay(delay); \ ++ else \ ++ cpu_relax(); \ ++ udelay(1); \ ++ } \ ++ if (!__ret) \ ++ __ret = (condition); \ ++ __ret; \ ++}) ++ + /* Loop-based definitions for assembly code. */ + extern void __loop_delay(unsigned long loops); + extern void __loop_udelay(unsigned long usecs); +--- a/arch/arm/include/asm/io.h ++++ b/arch/arm/include/asm/io.h +@@ -221,6 +221,34 @@ extern int pci_ioremap_io(unsigned int o + #endif + #endif + ++/* access ports */ ++#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) ++#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) ++ ++#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) ++#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) ++ ++#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) ++#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) ++ ++/* Clear and set bits in one shot. These macros can be used to clear and ++ * set multiple bits in a register using a single read-modify-write. These ++ * macros can also be used to set a multiple-bit bit pattern using a mask, ++ * by specifying the mask in the 'clear' parameter and the new bit pattern ++ * in the 'set' parameter. ++ */ ++ ++#define clrsetbits_be32(addr, clear, set) \ ++ iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) ++#define clrsetbits_le32(addr, clear, set) \ ++ iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr)) ++#define clrsetbits_be16(addr, clear, set) \ ++ iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) ++#define clrsetbits_le16(addr, clear, set) \ ++ iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr)) ++#define clrsetbits_8(addr, clear, set) \ ++ iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) ++ + /* + * IO port access primitives + * ------------------------- |