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authorYutang Jiang <yutang.jiang@nxp.com>2016-10-29 00:14:32 +0800
committerJohn Crispin <john@phrozen.org>2016-10-31 17:00:10 +0100
commitc6c731fe311f7da42777ffd31804a4f6aa3f8e19 (patch)
treed92c7296f82d46d1b2da30933a97595f6cb8ad66 /target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch
parenta34f96d6cf80c7c3c425076714d9c4caa67e3670 (diff)
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layerscape: add 64b/32b target for ls1043ardb device
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch')
-rw-r--r--target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch42
1 files changed, 42 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch b/target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch
new file mode 100644
index 0000000000..3dd0548b8c
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch
@@ -0,0 +1,42 @@
+From 6ef5cf7b8f6b86fb3856f3449f1ad431118e5c9d Mon Sep 17 00:00:00 2001
+From: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed, 22 Apr 2015 13:07:25 -0400
+Subject: [PATCH 33/70] arm64: add ioremap for normal cacheable non-shareable
+ memory
+
+[context adjustment]
+
+Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+Change-Id: Iab7413f182a64bd6ad4707dd1d6254d04f51a3b1
+Reviewed-on: http://git.am.freescale.net:8181/35486
+Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
+Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
+Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm64/include/asm/io.h | 2 ++
+ arch/arm64/include/asm/pgtable.h | 2 ++
+ 2 files changed, 4 insertions(+)
+
+--- a/arch/arm64/include/asm/io.h
++++ b/arch/arm64/include/asm/io.h
+@@ -171,6 +171,8 @@ extern void __iomem *ioremap_cache(phys_
+ #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
+ #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
+ #define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
++#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), \
++ __pgprot(PROT_NORMAL_NS))
+ #define iounmap __iounmap
+
+ /*
+--- a/arch/arm64/include/asm/pgtable.h
++++ b/arch/arm64/include/asm/pgtable.h
+@@ -74,6 +74,8 @@ extern void __pgd_error(const char *file
+ #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
+ #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
+ #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
++#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | \
++ PTE_ATTRINDX(MT_NORMAL))
+
+ #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
+ #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))