layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 67 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.4/1107-mtd-fsl-quadspi-disable-AHB-buffer-prefetch.patch b/target/linux/layerscape/patches-4.4/1107-mtd-fsl-quadspi-disable-AHB-buffer-prefetch.patch
new file mode 100644
index 0000000000..19dff6c92e
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/1107-mtd-fsl-quadspi-disable-AHB-buffer-prefetch.patch
@@ -0,0 +1,67 @@
+From 50aac689d5be0a086f076cd4bc8b14ee0b9ab995 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Tue, 8 Mar 2016 14:38:52 +0800
+Subject: [PATCH 107/113] mtd: fsl-quadspi: disable AHB buffer prefetch
+
+A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
+Affects: QuadSPI
+Description: With AHB buffer prefetch enabled, the QuadSPI may return
+incorrect data on the AHB
+interface. The buffer pre-fetch is enabled if the fetch size as
+configured either in the LUT or in
+the BUFxCR register is greater than 8 bytes.
+Impact: Only 64 bit read allowed.
+Workaround: Keep the read data size to 64 bits (8 Bytes), which disables
+the prefetch on the AHB buffer,
+and prevents this issue from occurring.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c |   29 +++++++++++++++++++++++------
+ 1 file changed, 23 insertions(+), 6 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -794,19 +794,36 @@ static void fsl_qspi_init_abh_read(struc
+ {
+ 	void __iomem *base = q->iobase;
+ 	int seqid;
++	const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
+ 
+ 	/* AHB configuration for access buffer 0/1/2 .*/
+ 	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
+ 	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
+ 	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
++
+ 	/*
+-	 * Set ADATSZ with the maximum AHB buffer size to improve the
+-	 * read performance.
++	 * Errata: A-009282: QuadSPI data prefetch may result in incorrect data
++	 * Workaround: Keep the read data size to 64 bits (8 bytes).
++	 * This disables the prefetch on the AHB buffer and
++	 * prevents this issue from occurring.
+ 	 */
+-	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+-			((q->devtype_data->ahb_buf_size / 8)
+-			<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
+-			base + QUADSPI_BUF3CR);
++	if (devtype_data->devtype == FSL_QUADSPI_LS2080A ||
++	    devtype_data->devtype == FSL_QUADSPI_LS1021A) {
++
++		qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
++				(1 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
++				base + QUADSPI_BUF3CR);
++
++	} else {
++		/*
++		 * Set ADATSZ with the maximum AHB buffer size to improve the
++		 * read performance.
++		*/
++		qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
++				((q->devtype_data->ahb_buf_size / 8)
++				<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
++				base + QUADSPI_BUF3CR);
++	}
+ 
+ 	/* We only use the buffer3 */
+ 	qspi_writel(q, 0, base + QUADSPI_BUF0IND);