layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 112 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.4/1104-mtd-fsl-quadspi-Add-quad-mode-for-flash-n25q128.patch b/target/linux/layerscape/patches-4.4/1104-mtd-fsl-quadspi-Add-quad-mode-for-flash-n25q128.patch
new file mode 100644
index 0000000000..daf34e3388
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/1104-mtd-fsl-quadspi-Add-quad-mode-for-flash-n25q128.patch
@@ -0,0 +1,112 @@
+From 23cd071c47c064d56921975d196dc22177069dea Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Wed, 24 Feb 2016 15:14:01 +0800
+Subject: [PATCH 104/113] mtd: fsl-quadspi: Add quad mode for flash n25q128
+
+Add some lut_tables to support quad mode for flash n25q128
+on the board ls1021a-twr and solve flash Spansion and Micron
+command conflict.
+In switch {}, The value of command SPINOR_OP_RD_EVCR and
+SPINOR_OP_SPANSION_RDAR is the same. They have to share
+the same seq_id: SEQID_RDAR_OR_RD_EVCR.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c |   47 ++++++++++++++++++++++++++++---------
+ 1 file changed, 36 insertions(+), 11 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -207,9 +207,9 @@
+ #define SEQID_RDCR		9
+ #define SEQID_EN4B		10
+ #define SEQID_BRWR		11
+-#define SEQID_RDAR		12
++#define SEQID_RDAR_OR_RD_EVCR	12
+ #define SEQID_WRAR		13
+-
++#define SEQID_WD_EVCR           14
+ 
+ #define QUADSPI_MIN_IOMAP SZ_4M
+ 
+@@ -393,6 +393,7 @@ static void fsl_qspi_init_lut(struct fsl
+ 	int rxfifo = q->devtype_data->rxfifo;
+ 	u32 lut_base;
+ 	int i;
++	const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
+ 
+ 	struct spi_nor *nor = &q->nor[0];
+ 	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
+@@ -489,16 +490,26 @@ static void fsl_qspi_init_lut(struct fsl
+ 	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
+ 			base + QUADSPI_LUT(lut_base));
+ 
++
+ 	/*
+-	 * Read any device register.
+-	 * Used for Spansion S25FS-S family flash only.
++	 * Flash Micron and Spansion command confilict
++	 * use the same value 0x65. But it indicates different meaning.
+ 	 */
+-	lut_base = SEQID_RDAR * 4;
+-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
+-			LUT1(ADDR, PAD1, ADDR24BIT),
+-			base + QUADSPI_LUT(lut_base));
+-	qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
+-			base + QUADSPI_LUT(lut_base + 1));
++	lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
++	if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
++		/*
++		* Read any device register.
++		* Used for Spansion S25FS-S family flash only.
++		*/
++		qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
++			    LUT1(ADDR, PAD1, ADDR24BIT),
++			    base + QUADSPI_LUT(lut_base));
++		qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
++			    base + QUADSPI_LUT(lut_base + 1));
++	} else {
++		qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
++			    base + QUADSPI_LUT(lut_base));
++	}
+ 
+ 	/*
+ 	 * Write any device register.
+@@ -511,6 +522,11 @@ static void fsl_qspi_init_lut(struct fsl
+ 	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
+ 			base + QUADSPI_LUT(lut_base + 1));
+ 
++	/* Write EVCR register */
++	lut_base = SEQID_WD_EVCR * 4;
++	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
++		    base + QUADSPI_LUT(lut_base));
++
+ 	fsl_qspi_lock_lut(q);
+ }
+ 
+@@ -523,8 +539,15 @@ static int fsl_qspi_get_seqid(struct fsl
+ 	case SPINOR_OP_READ_FAST:
+ 	case SPINOR_OP_READ4_FAST:
+ 		return SEQID_READ;
++	/*
++	 * Spansion & Micron use the same command value 0x65
++	 * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
++	 * Micron: SPINOR_OP_RD_EVCR,
++	 * read enhanced volatile configuration register.
++	 * case SPINOR_OP_RD_EVCR:
++	 */
+ 	case SPINOR_OP_SPANSION_RDAR:
+-		return SEQID_RDAR;
++		return SEQID_RDAR_OR_RD_EVCR;
+ 	case SPINOR_OP_SPANSION_WRAR:
+ 		return SEQID_WRAR;
+ 	case SPINOR_OP_WREN:
+@@ -550,6 +573,8 @@ static int fsl_qspi_get_seqid(struct fsl
+ 		return SEQID_EN4B;
+ 	case SPINOR_OP_BRWR:
+ 		return SEQID_BRWR;
++	case SPINOR_OP_WD_EVCR:
++		return SEQID_WD_EVCR;
+ 	default:
+ 		if (cmd == q->nor[0].erase_opcode)
+ 			return SEQID_SE;